Cutting the power of IoT transmitters
Researchers in Japan have developed a technique that could remove a power-hungry block from wireless transmitters for the Internet of Things (IoT).
The team at Institute of Science Tokyo have combined three techniques to eliminate a key block, the COordinate Rotation DIgital Computer (CORDIC). This is being shown at the ISSCC conference in the US this week.
The expansion of the IoT is driving demand for highly power-efficient transmitters as most devices are battery-operated and the increasing use of AI is driving up data rates and power consumption..
Many transmitters represent input data in polar coordinates—amplitude and phase—which is then transmitted by precise adjustment of the output radio wave’s polar coordinates. However, determining these polar coordinates relies on the CORDIC.
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The CORDIC generates multi-bit amplitude and phase signals that require corresponding modulators. However these can suffer from linearity issues, limiting data rates and making it challenging to balance efficiency and data rate. Enhancing one often compromises the other; for example, linearity calibration techniques such as digital pre-distortion (DPD) can resolve linearity problems for higher data rate but at the expense of additional power consumption.
“The first proposed technique employs Delta-Sigma Modulators (DSMs) to re-encode the input data. Instead of directly calculating the polar coordinates of the input x and y signals, two DSMs convert them into 3-level signals,” said Professor Kenichi Okada at Science Tokyo. “Because these 3-level outputs yield only nine distinct amplitude-phase combinations, a simple nine-state look-up table (LUT) can effectively determine the amplitude and phase.”
This reduces the bit count with a 2bit amplitude and 3bit phase value with the second technique for linear amplitude and third for phase modulation.
In conventional multi-bit amplitude and phase modulation schemes, device matching plays a major role in accurately generating intermediate values between zero and the peak relies. However, mismatches arising during this production disrupt the modulation linearity.
Instead, the 2bit amplitude signal is further quantized to 1bit, preventing increased in-band noise. The 1bit amplitude controls the transmitter output to toggle between zero and peak amplitudes without any intermediate states, facilitating complete linearity in the transmitter’s amplitude.
As the phase control code has only 3bits, eight phases separated by 45° each are required. Rather than interpolating phases from 0° to 360°, by using the rising and falling edges of a square wave running at four times the carrier frequency, the eight phases were generated. Multiplexing the different edges of the square wave forms the output phase.
The team tested their ideas by implementing the proposed digital transmitter using a 65nm CMOS process and compared its performance with other state-of-the-art designs.
“By applying these techniques, we achieved top-tier power efficiency and data rates among conventional transmitters, without compromising one for the other, thanks to our CORDIC-less polar transmitter architecture,” said Okada.
Proceedings of the 2025 IEEE International Solid-State Circuits Conference (ISSCC).
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