Cypress Aims Low-Pin Memory at Automotive, IoT

Cypress Aims Low-Pin Memory at Automotive, IoT

Technology News |
By Christoph Hammerschmidt

Cypress Semiconductor’s recent update to its HyperRAM memory DRAM device is addressing the automotive industry’s preference for fewer moving pieces with a lower pin count. The company is now sampling its new high-speed, self-refresh DRAM based on its low-pin-count HyperBus interface.

The 64Mb HyperRAM is designed to serve as an expanded scratchpad memory for rendering of high-resolution graphics or calculations of data-intensive firmware algorithms in a wide array of automotive, industrial and consumer applications, said Rainer Hoehler, VP of the flash business unit at Cypress, in an interview with EE Times. Microcontrollers often do not have enough integrated memory for high-resolution graphics or data-intensive firmware algorithms.

Hoehler said the new HyperRAM is best used when paired with Cypress HyperFlash NOR flash memory in an embedded system—both the flash and RAM reside on the same 12-pin HyperBus. The combination reduces the pin count by at least 28 pins, he said, compared to traditional systems using SDRAM and Dual-Quad SPI solutions that require upwards of 41 pins on two buses for data transactions, which simplifies designs and lowers PCB cost. The new Cypress HyperRAM devices operate with a read/write bandwidth of up to 333 MBps and are available in 3V and 1.8V supply voltage ranges.

Cypress’ HyperRAM supports a common footprint
with its HyperFlash, using only 12 pins for data transactions.

The embedded systems-focused Cypress is seeing more demand for higher performance for interfaces, said Hoehler, but with lower pin counts, both in automotive applications and IoT, particularly industrial IoT, where more process power is required from a microcontroller. “They are running out of on-chip RAM, but they want to keep a small pin count and a small PCB with high read and write bandwidth.

He said designers are looking to reduce overall system cost by combining DRAM and flash in a single package if possible. Cypress’ HyperRAM and HyperFlash are addressing a gap between systems that need high performance DRAM with lots of pins on one side and flash on the other side. Hoehler said the company has focused on how to generate one footprint that works with different memory types, allowing for single SPI or quad SPI HyperFlash, in a single package, for example, and giving designers lots of flexibility.

In addition to flexibility and a smaller footprint, HyperRAM does address power consumption concerns, although Hoehler said it’s a not a major pressure for the device, given that low power consumption is already part of the embedded memory mindset. It’s also designed to handle the wide temperature ranges common to automotive as well as being able to perform well in fan-less enclosures.

For now the latest HyperRAM comes in 64Mb densities, said Hoehler, but Cypress has a roadmap for higher densities. He is also bullish on the opportunities to integrate IoT technologies recently acquired from Broadcom, such as WiFi and Bluetooth connectivity, rather than just doing the next memory device.

HyperRAM itself, of course, is also the result of the acquisition of Spansion by Cypress. Spansion first announced HyperRAM early last year, after announcing its HyperBus interface and HyperFlash in 2014, designed to for use in SoCs and microcontrollers where both RAM and flash are connected to the same Hyperbus Interface as an alternative to the commonly used options of SRAM or PSRAM using a parallel bus with more pins.

Cypress is also bullish about integrating IoT technologies
it acquired from Broadcom into its automotive offerings.

Jim Handy, principal analyst with Objective Analysis, believes that Cypress no longer wants to be just a memory company. “They want to shape themselves into a company that provides solutions for a certain class of application,” he said in a telephone interview with EE Times. “With a minimal engineering effort, customers get want they want and get locked into a Cypress solution.”

Handy said car manufacturers would ideally prefer to everything with a microcontroller without the need for any external memory. “The car guys want to reduce the number of chips.” For all intents and purposes, chips and pins contribute to the number of moving parts in a vehicle, so the more things you have in a car, the more potential reliability issues are possible, he said. “Connectors are the big bugaboo. Automakers want the minimum number of parts to get what they need done in the car.”

—Gary Hilson is a general contributing editor with a focus on memory and flash technologies for EE Times where this article has been published previously.

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