D-Wave looks to large scale gate-based quantum computer
D-Wave Systems is using its annealing quantum computer to help design and build large fault tolerant gate-based systems.
Trevor Lanting, Chief Development Officer at D-Wave, talks to Nick Flaherty about the plans for the future, including how the company is using its existing quantum computers to design the next generation of machines.
D-Wave was one of the earliest pioneers of quantum technology and already has a superconducting quantum computer system with 5000 qubits handling annealing algorithms. This is based on an array of tiny loops of metal that contain superconducting Josephson junctions. The challenge is connecting the loops together, which is achieved with couplers.
“The Advantage is our fifth generation of annealing quantum computer with 15 way connectivity, 40,000 couplers,” Lanting tells eeNews Europe. “We go below 10-20mK for superconducting but also to reduce the thermal fluctuations to minimise perturbations.”
“Two years ago we took a fresh look at commercial paths to commercial gate-based quantum systems. There’s a lot of innovation around error correction codes and this can be coupled with all our advances in cryogenics which carries over to the gate systems.”
The company is using its annealing quantum computer to design the next generation of error-corrected gate-based systems. Rather than the current Noisy Intermediate-Scale Quantum (NISQ) systems, this will require thousands of physical qubits to deliver a few logical qubits.
“We are not interested in building a NISQ technology,” he said. “To get to true quantum utility you need a fault tolerant topology with error correction built in from the beginning and that’s a key part of the gate model succeeding. The control and requirements on the qubits are much more stringent than for annealing.”
D-Wave is using the same qubit structures and data systems but with different coupling and magnetic control systems.
“We have a large scale readout technology that works so we have adapted that. We have had prototype processors in the cloud for two years now. One of those has 1200 qubits with 20 way connectivity and we have in situ measurements that show we double the coherence time as we wanted to make sure we understood the performance.
The company is characterising 5000 qubit processors over the next few months but the scale will be at least 5000 but still to be determined. This is about Increasing the connectivity and coherence of the qubits,” he said.
Flux-based qubits
“At the core we are using a flux-based qubit, or fluxonium, for the gates,” said Lanting. “Parametrically, and topologically its very similar to the annealing qubits.”
“We have a loop of superconducting wire with Josephson Junctions for nonlinaearlity with a coupler. Quantised states of current circulate one way or the other, and a magnetic field mediates the interaction of the qubits.
“If you make the mutual inductance tunable you couple the devices and then you send magnetic signals into the loop to set up the qubit. This needs higher bandwidth control, although for the flux qubits this is at VHF frequencies of hundreds of MHz rather than GHz [for other technologies].”
The final opportunity is the coherence of the gate, how long the qubits stay entangled to perform a calculation. “We have achieved coherence times of several hundred microseconds ( T1) times.”
“We have no near term timeline for a product with the gate model. We recently completed a layout and design of a logical qubit so we have a way to lay it out that we think will scale and we are moving onto the rest of the design. The majority of the on chip control is built into the plans for the gate model.”
Here they are exploring using the annealing systems for design.
“Even when we are laying out our circuits its a hard optimisation problem to minimise the wiring, the real estate, so having an optimisation co processor would be very helpful. We have a couple of examples, for wire bonding diagrams with sequencing so we have played around with the quantum system but not used this in a production sense,” he said.
It plans to carry on the annealing systems as it develops the gate-model machines over the next few years, and sees the power consumption as a key advantage.
“We see the technologies as complementary, with annealing for optimisation while we think the sweet spot for gate systems is for simulation of materials. Each has its sweet spots.”
A combination of annealing and gate-based machines would need to be driven by a use case or applications. “In the near to medium term these would be separate systems but as the industry starts to understand hybridisation there is potential. When you delve into any complicated business problem all you find is optimisations,” he says.
“We are using off the shelf cryogenics and have a record continuous uptime of 5 years at a customer site. The on chip power dissipation is very small with minimal static or dynamic power dissipation. The overall power draw is 12 to 15kW and that has stayed the same over 5 processor generations, so its not really increasing. The main power draw is the fridge itself and the rest is essentially a rounding error.”
“Increasingly this is a key advantage for the systems we are using.”
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