DCD’s D16950 offers a new spin on a familiar function

DCD’s D16950 offers a new spin on a familiar function

New Products |
By eeNews Europe

DCD’s UART IP Core performs a serial-to-parallel conversion on data characters received from a peripheral device or a MODEM. And for those who need more, the D16950 enables also parallel-to-serial conversion on data characters received from the CPU. The processor can read a complete status of the UART at any time during the functional operation. Reported status information includes the type and condition of transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing or break interrupt). – The D16950 includes a programmable baud rate generator, which is capable of dividing the timing reference clock input by divisors of 1 to (216-1) and to produce a n × clock for driving the internal transmitter logic. Provisions are also included to use this n × clock to drive the receiver logic.

The D16950 UART IP Core is equipped with a complete MODEM-control capability and a processor-interrupt system. Interrupts can be programmed in accordance to specific requirements, minimising computing required to handle the communications link. The D16950 core includes all other UART’s (16450, 16550, 16650 and 16750) features and additional functions. ICR registers give additional capabilities of UART configuration. The data transmission can be synchronised by an external clock connected to the RI (for receiver and transmitter) or the DSR (only for receiver) pin. The NMR register enables a 9-bit mode transmission, with or without special character. Writing and reading from/to FIFO may be controlled by trigger level registers, with any value set from 1 to 127.

DCD’s IP Core implements an auto flow control feature, which can significantly reduce software overload and increases the system efficiency, by controlling serial data flow through the RTS output and the CTS input signals.

The D16950 is suitable for applications, where the UART core and the microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip. It’s also a proprietary solution for a standalone implementation, where several UARTs are required to be implemented inside a single chip and driven by some off-chip devices. Thanks to a universal interface, the D16950 core implementation and verification are very simple, just by eliminating a number of clock trees in the complete system.

DCD’s IP Core includes a fully automated test bench with complete set of tests, allowing easy package validation at each stage of SoC design flow. The D16950 is also a technology independent design, that can be implemented in a variety of process technologies.


The features

Key Features:

Software compatible with 16450, 16550,16650,16750 and 16950 UARTs

Configuration capability

Separate configurable BAUD clock line

Majority Voting Logic

Two modes of operation: UART mode and FIFO mode

In the FIFO mode transmitter and receiver are each buffered with 128 byte FIFO to reduce the number of interrupts presented to the CPU

In UART mode receiver and transmitter are double buffered to eliminate the need for precise synchronization between the CPU and serial data

Configurable FIFO size up to 512 levels

Adds or deletes standard asynchronous communication bits (start, stop and parity) to or from the serial data

Independently controlled transmit, receive, line status and data set interrupts

False start bit detection

16 bit programmable baud generator

Independent receiver clock input

MODEM control functions (CTS, RTS, DSR, DTR, RI, DCD)

Programmable Hardware Flow Control through RTS and CTS

Programmable Flow Control using DTR and DSR

Programmable in-band Flow Control using XON/XOFF

Programmable special characters detection

Trigger levels for TX and RX FIFO

Interrupts and automatic in-band and out-off-band flow control

Fully programmable serial-interface characteristics:

5-, 6-, 7-, 8- or 9-bit characters

Even, odd, or no-parity bit generation and detection

1-, 1.5-, or 2-stop bit generation

Internal baud generator

Detection of bad data in receiver FIFO

Clock prescaler from 1 to 31,875

Enhanced isochronous clock option

9- bit data mode

Software reset

Complete status reporting capabilities

Line break generation and detection. Internal diagnostic capabilities:

Loop-back controls for communications link fault isolation

Break, parity, overrun, framing error simulation

Full prioritized interrupt system controls

Available system interface wrappers:


Altera Avalon Bus

Xilinx OPB Bus

Fully synthesisable

Static synchronous design and no internal tri-states

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