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Deals bring PCIe 6.0 and HBM3 to FPGA prototyping for Data Centre and AI chips

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By Nick Flaherty


Avery Design Systems has launched native FPGA speed adapters for PCIe 6.0 and advanced memory technologies for LPDDR5 and HBM3, as well as verification support for the HBM3 Interface Standard. Rambus is also using Avery’s HBM3 memory model to verify its HBM3 PHY and Controller Subsystem

The PCIe 6.0 offering for the speed adapter is a result of a partnership with S2C EDA and its Prodigy Logic Matrix LX2 System for high-performance ASIC/SoC prototyping, and enables system validation of the latest data centre, NVMe and embedded storage, and AI/ML SoC designs that incorporate the latest high speed interconnect and memory technologies.

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“Avery speed adapters accelerate software development, hardware verification and system validation by enabling FPGA prototypes to be integrated with native system platforms to allow validation to be performed at actual system run speeds. This approach overcomes the inherent performance limitations of multi-FPGA representations of System SoCs and that lack support for latest generation of PCIe or memory technologies,” said Chris Browy, VP sales and marketing of Avery in Tewkesbury, UK. “By partnering with S2C we address the ever-increasing complexity and performance requirements in large-scale SoC designs with a solution that provides accurate and timely verification methodologies.”

“FPGA prototyping, in essence, is about high-performance validation. The high-performance quality not only accelerates the design cycle but also enables hardware and software bugs to be caught through the interaction with real-world data,” said Ying Chen, VP sales and marketing of S2C. “The Logic Matrix LX2 is a high-density FPGA prototyping platform with eight Xilinx VU19P FPGAs designed to address the needs for both capacity and performance in complex SoC designs. By partnering with Avery, our customers can now easily validate against the latest generations of PCIe and memory interfaces.”

Avery supports a spectrum of system-level validation and hardware accelerated solutions that complements its full line of leading SystemVerilog/UVM Verification IP. This includes virtual host and embedded platform co-simulation using QEMU and Arm Fast Models as well as SimAccel co-emulation software tools and system IP targeted to any Xilinx FPGA boards.

Next: Rambus HBM3

 


The Rambus HBM3 Memory Subsystem, comprised of an HBM3 PHY and HBM3 Controller, is optimized for systems that require a high-bandwidth, low-latency memory solution. This includes applications in AI/ML training, graphics and high-performance computing (HPC). The subsystem supports data rates up to 6.4 Gbps per data pin and features 16 independent channels, each containing 64 bits for a total data width of 1024 bits. At maximum data rate, this provides a total interface bandwidth of 1075.2 GB/s.

Rambus uses Avery’s memory model to verify its HBM3 PHY and controller and includes these memory models in its customer deliveries to enable out-of-the-box simulations with the delivered IP. Customers can then license the Avery memory models for use in full SoC verification.

“We deliver fully integrated and verified memory subsystems in order to meet our customers’ time-to-market and quality demands. Avery has been a trusted partner and plays a critical role in helping us to ensure our memory subsystems perform as promised,” said Brian Daellenbach, senior director of Memory & MIPI Controllers, Interface IP at Rambus.

Avery offers a complete functional verification platform based on its robustly tested verification IP (VIP) portfolio that enables pre-silicon validation of design elements. Its HBM3 offering includes memory models, protocol checkers, performance analysis, and compliance test-suites utilizing a flexible and open architecture. HBM2E and HBM3 speed adapters are also available for FPGA prototyping platforms.

“Our mutual customers need early access to verified models of the latest standards, as well as a verification platform to enable a reliable verification methodology. Our collaboration with Rambus allows developers to stay ahead of the curve as new standards emerge. We are pleased to be able to deliver an HBM3 verification solution, which enables our customer to develop compute-intensive SoCs in advanced processes with confidence,” said Chris Browy, vice president of sales/marketing at Avery.

www.avery-design.com; www.rambus.com; www.s2ceda.com

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