Debug for RISC-V; Segger J-Link supports SiFive’s Coreplex IP
SiFive was founded by the inventors of RISC-V – Yunsup Lee, Andrew Waterman and Krste Asanovic – with a mission to democratize access to custom silicon. In its first six months of availability, its HiFive1 software development boards have been delivered to thousands of developers in over 40 countries, making (Segger asserts) SiFive Coreplex IP the de facto leader for RISC-V cores.
All current J-Link models now support debugging of RV32 RISC-V cores. This includes support from Segger’s GDB Server, which is part of the J-Link software package that supports SiFive’s free Eclipse-based Freedom Studio. J-Link’s high performance and functionality allows it to be easily used and it provides reliable, professional support to RISC-V cores. Features also include a direct Flash memory download via an open flash loader interface giving SiFive and the RISC-V ecosystem access to Segger’s catalogue of supported flash devices. For systems running code from flash memory instead of RAM, there is an unlimited number of breakpoints not only in RAM, but also in Flash (with higher end J-Link PLUS, J-Link Ultra + and J-Link PRO models).
The low-cost J-Link EDU version allows students and hobbyists to use professional debug technology with RISC-V. Using J-Link with RISC-V is demonstrated by downloadable examples, here.
Segger; www.segger.com/products/debug-probes/j-link/ and www.segger.com/downloads/jlink
SiFive; www.sifive.com
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