Define drain-current conditions when calculating power for multi-core SoCs
The automotive electronics meant for safety applications are increasingly implementing multi-CPU architectures with on-chip redundancy to safeguard applications using minimal software overhead. On one hand, having on-chip redundancy is good for safety measures, but on the other hand it has attached baggage like higher die-area, higher noise, higher power consumption, etc.
This article discusses the factors that should be considered when calculating the power numbers of such SoCs. These factors if not decided judiciously may lead to inaccurate power numbers in the product datasheet, which could result in lost sales or customer dissatisfaction.
Power consumption of a device under typical run conditions is one of the important parameters specified on a datasheet. In the case of SoCs, the power consumption number depends on multiple factors like frequency of operation, modules enabled during the operation, CPU and DMA (direct memory access) operations with cache enabled/disabled, etc. For multi-CPU (multi-core) SoCs, another factor is whether the CPUs are working in lock-step or a decoupled parallel mode.
This feature discusses the various factors considered to define the typical Run-Idd (drain current) conditions (TRC) for the power measurement. This is a very important step before proceeding to make measurements and justify the power numbers on the datasheet. The analysis presented here is for a dual-CPU SoC, but is well applicable to all multi-CPU SoCs.
The full article, which gives an overview of Freescale’s dual-CPU architecture, typical run conditions and their influence on current consumption, can be read here (courtesy EE Times Automotive DesignLine)
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