Deriving design margins for successful timing closure
With the fast developing technology, the complexity of design is increasing day by day. To meet lower technology challenges and to achieve good silicon yield, SOC design flows have been enhanced and have introduced more number of design implementations steps. With every implementation step which takes design towards realistic working silicon, SOC design timing performance degrades due to various factors which were not apparent at previous implementation step. Thus it is very important to have a right estimate of design frequency since first stage of design implementation. The important parameter which makes it possible are called Design Margins.
Design margins
Design Margins are the extra pessimism introduced in terms of design uncertainty which covers the expected timing hit of every stage in implementation cycle so as to achieve targeted frequencies well in time. It is very much required to have a right estimate of design margins.
Underestimated design margins
The scope of timing optimization reduces as we move down the implementation flow. So it becomes very important to judge the setup timing degradation hit in advance to achieve the targeted design frequency at the end. If design margins are not enough for any stage, it will not be possible to close design targeted frequencies. It will directly impact Design Performance.
Overestimated design margins
For any stage if design margins are chosen overly pessimistic, it will result in extra timing optimization which might not be required. This results in extra consumption of silicon area and power. The impact is SOC designs would not be cost effective, also bad power numbers may result in poor battery life.
General SOC flow and impact on design frequency
Figure 1 shows general SOC flow which starts from synthesis and concludes at noise closure.
The first step of physical design SOC closure flow is synthesis. During synthesis stage the exact timing degradation due to placement, clock skew, inter connect delays and noise is not known. So, during synthesis stage timing uncertainty corresponding to above parameters has to be modeled properly for efficient timing closure. So, effective frequency for a timing path is maximum at synthesis stage. Now, at placement stage the designer is aware of timing degradation because of placement but not due to clock skew, inter connect delays and noise. So, at placement stage timing uncertainty need not include placement margin. Based on the above reasoning, it is clear that timing uncertainty should be different at different stages of the design.
Timing margins (uncertainties) for different design stages
PLL Jitter
PLL Jitter value, which indicates the edge shift of PLL clock from one edge to another, is very crucial factor while timing setup path. It can either be considered in uncertainty or can be made part of clock period. Making it a part of clock period make more sense as it should be adjusted in case of multi cycle paths
2 Types:
Cycle2Cycle Jitter: Jitter between 2 consecutive edges
Long Term Jitter: It provides maximum possible jitter to be considered for multiple cycle paths.
To maintain pessimism in correct way, it is better to make it a part of clock period. And for multi cycle path it can always be checked whether [N x (cycle2cycle jitter)] or long term jitter should be considered, where N is the multi cycle value.
Half Cycle Jitter: Half cycle jitter specifies the edge shift between rise and fall edges. All half cycle paths should be closed after factoring this half cycle jitter uncertainty
Placement timing jump
Since physical location of design instances is not known during logical synthesis stage, the timing degradation is bound to happen while moving from synthesis to placement stage. Moreover the synthesis tool generally has better logic optimization capability, so it is better to keep extra timing margin at synthesis stage (which is removed at placement stage), to negate the timing degradation impact because of placement.
Clock skew
Clock skew determines the allowed skew while clock tree synthesis. Too low skew numbers can lead to increase in clock latency and can impact us with increased OCV effect and dynamic power, and at the same time too relaxed skew targets can cause too many hold violations.
Maximum Range can be figured out by using following formula for a typical hold critical path.
Skew (max) <= CK-Q Delay of Flop 1 + net delay from Q of 1st flop to input (D/SDI) of 2nd flop Hold time of second flop
Above value should be justified with minimum latency of clock.
Note:
- CTS tools generally work in single operating mode. But, as the signoff analysis is always done in OCV mode, clock skew should be measured after switching to OCV mode.
- In case of clocks with different top level source latency, we also need to have inter clock skew uncertainty.
OCV Margin
Various factors for On Chip Variations are
- IR drop.
- Layer to layer metallization mismatch.
- CMP induced metallization variations.
- Transistor level Vth mismatch.
- Transistor level mobility mismatch.
- Intra die temperature variation.
- Toggling activity mismatch (related to transistor aging).
To cover the factors listed above, timing derates are applied for both setup and hold check. Considering the average clock latency and taking care of CPPR pessimism, OCV impact can be estimated. It should made part of uncertainty at pre CTS stage to negate the setup timing impact visible after the application of actual OCV derates at post CTS stage.
Noise margin
Once a design is timing clean after routing stage, crosstalk analyses can induce some change in net & cell delays. A margin needs to be set for this as well during setup & hold optimization.
Design stages & uncertainties
Above discussed factors define the required timing margins to be applied at the early design stages for successful timing closure. With every progressive design stage completion, timing margins reduce. Following is the way to model it with every design stage.
if {$stage == "synth"} {
set uncertainty [expr $NOISE_MARGIN + $OCV_MARGIN + $CLOCK_SKEW + $PLACE_MARGIN]
} elseif {$stage == "place"} {
set uncertainty [expr $NOISE_MARGIN + $OCV_MARGIN + $CLOCK_SKEW]
} elseif {$stage == "cts"} {
set uncertainty [expr $NOISE_MARGIN + $OCV_MARGIN]
} elseif {($stage == "ocv"} {
set uncertainty [expr $NOISE_MARGIN]
} elseif {$stage == "si" || $stage == "signoff"} {
set uncertainty 0
} else {
error "The variable ‘stage’ is NOT set properly"
}
*Jitter is assumed to be modeled in time period
Design margins for partitioned block
In designs where blocks are implemented separately, it is very important to consider extra inter block margin along with the block uncertainty in block constraints because new timing violations can pop up due to the partitioning approach. There can be four types of timing paths across block.
- Intra clock reg to reg path (b/w B & C)
- Input to reg path
- Inter clock reg to reg path (b/w A & B)
- Register to output path.
For Path type 1, we have already discussed how uncertainties will be modeled with respect to various design stages.
Inter clock uncertainty
To cover Path type 2-3-4, we need extra uncertainty that will consider the uncertainty required for top level design closure.
Top level uncertainty depends on the top level skew, OCV effect & noise effect.
Y – Top level allowed skew between different clocks (inter clock skew).
V – Noise effect (margin) on block from top.
S – Top level OCV impact on clocks. It can be judge by derating the expected uncommon clock path at top level.
Considering the above factors,
For Path Type 3, the updated uncertainty is
For Path Type 2 & 4, the updated uncertainty is
The above discussed top level additional uncertainty needs to be added while blocks level closure irrespective of the block level stage.
Added complexities due to timing modes merging
Consider a partitioned block having two clocks (clk1 and clk2) and 2 timing modes (M1 and M2)
Following are the valid worst case timing paths that cover the complete timing signoff within the partitioned block:
- Clk1 -> Clk1 @ 500 Mhz ( Time period = 2 ns )
- Clk2 -> Clk2 @ 200 Mhz ( Time period = 5 ns )
- Clk1 -> Clk2 @ 400 Mhz ( Time period = 2.5 ns )
- Clk2 -> Clk1 @ 400 Mhz ( Time period = 2.5 ns )
To meet timing requirement for the above block, following approaches can be followed:
- The basic approach is to create 2 different timing modes and meet timing in both the modes. This approach is optimal for area and power but may not be optimal for design cycle time as it can lead to multiple iterations.
- The better approach will be to create a single mode having Clk1 frequency at 500 Mhz (Time period = 2 ns) and Clk2 frequency at 250 Mhz (Time period = 4ns). In addition to this, a negative uncertainty (which makes timing path optimistic) of 0.5 ns is applied between Clk1 & Clk2 and a negative uncertainty of 1.0 ns is applied between Clk2 & Clk2. In this way, all the valid timing requirement of partitioned block can be met in a single mode without any extra pessimism.
Conclusion
The above discussed design margins are technology dependent and are different at various stages of the design (maximum at initial and minimum at final stages of the design). These margins if applied optimally will help in efficient timing closure of the design to achieve higher yield without having any negative impact on area, power and overall design cycle time.
About the authors:
Ateet Mishra
Staff Design Engineer
Ateet Mishra is a staff design engineer at Freescale India, where he has worked for eight years. He has experience in static-timing analysis, RTL to Timing Closure. He has successfully taped out multiple SOCs in various technology ranging between C40 to 250um.
A
mol Agarwal
Lead design engineer
Amol Agarwal is working with Freescale Semiconductor as Lead Design Engineer and has experience of more than 7 years. He is currently working in physical design team at Freescale with STA & Synthesis as area of specialization. He has been involved in several block-level and chip-level designs in technology ranging from 250nm to 40nm.
Abhishek Mahajan
Design Engineer
Abhishek Mahajan has four years of experience in various domains such as logical and physical Synthesis, Static Timing Analysis, Place and Route and static low power verification.
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