Design a VRM with perfectly flat output impedance in 5 seconds or less

Technology News | August 16, 2015

By eeNews Europe

Any discussion of power integrity includes a great deal of emphasis on the concept of target impedance and flat impedance requirements. But how do we design a voltage regulator module (VRM) specifically for flat impedance? This article will address not only that specific question, but how to accomplish it in 5 seconds or less.

I’m assuming that you haven’t computed the required target impedance yet, since that’s the tough part of this design problem. If you already know the design target impedance, you’re in luck as you fall into the “…..or less” category and can go directly to step 2. I know you’re skeptical, but since this is only a 5 second design, I’m hoping you’ll bear with me to see that I’m serious. While it will take some time to explain the process, at the end I’ll show you how to complete the process in less than 5 seconds.

The use of a current mode or current mode emulation topology significantly eases the design process, while also reducing the control loop complexity. While there are many devices to choose from, this particular article uses the Texas Instrument LM25116 as an example, since I have the evaluation board here and also because this particular evaluation board requires minimal modifications to achieve the desired flat impedance. The LM25116 is an emulated peak current mode controller, which also includes the required slope compensation and current waveform slope. These are set using a single, easily calculated capacitor.

This design process only requires a simple 2-port impedance measurement to verify the impedance flatness, though several other simple measurements are strongly suggested. The final design is easily “tweaked” using chip components to fine tune the impedance once it is constructed and why this fine tuning is necessary is also discussed.

Determining the Target Impedance
Assuming you know the voltage and current requirements of the VRM, the typical target impedance calculation is used to establish the output impedance of the VRM.
Using a 12Vinput 3.3V/10A output VRM requirement as an example, the target impedance is calculated as:

This is the MAXIMUM allowable impedance. In order to allow for component tolerances and to provide sufficient margin for switching ripple and dynamic load demands, the design target impedance is typically set much lower. A worst-case analysis assures the maximum is not exceeded. In this example, the nominal design target impedance is set to 14mΩ, determined, in part, to minimize the modifications to the evaluation board, which are somewhat difficult.

The Most Crucial Step
We’re most of the way through our VRM design now, with a single calculation needed to determine the fundamental VRM characteristic, transconductance. The current mode converter is the simplest to implement, since it can be represented as a transconductance block. The VRM output impedance is directly related to the transconductance (Gfs) by the relationship:

A simple simulation will prove that this solution results in the desired impedance over an infinite frequency range. The simulation schematic is shown Figure 1 and the simulated output impedance is shown in Figure 2.

Figure 1 A 70A/V transconductance source connected with negative feedback (note the negative sign in SRC1). SRC2 is an AC signal used to monitor the frequency dependent output impedance.

Figure 2 The simulation result shows a perfectly flat 14mΩ impedance as promised, confirming the relationship between impedance and transconductance.

In an ideal world, the VRM design really would be this simple, and we would be finished. In the real world, there are a few limitations and restrictions that will take just a bit more effort to solve. We can get through a practical design within a few minutes or by automating the process in a simulator in a few seconds.

Practical Limits
The design procedure to address these limitations is straightforward:
1.    Determine output capacitance and effective series resistance (ESR) required and select the capacitor
2.    Determine the power stage transconductance (usually based on current limit, RDSon, or DCR)
3.    Determine error amplifier gain and pole frequency
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4.    Determine output inductor
5.    Determine ramp capacitor for current mode emulated designs or slope compensation for standard current mode control
6.    Measure output impedance and fine-tune as necessary

We have already established that the VRM requires a transconductance of 70 to provide a 14mΩ impedance. The first issue is that the control loop bandwidth cannot be infinite, so it must be restricted to a realistic bandwidth. In order to avoid the odd behaviors near the switching frequency, a practical limit for the frequency is 1/10th to 1/6th of the switching frequency. Above the bandwidth, the capacitor controls the impedance, so the capacitor ESR is equal to the target impedance, 14mΩ in our example.

Output Capacitor
The switching frequency is an obvious tradeoff, since higher switching frequency results in smaller capacitors and inductors, while also resulting in higher losses. The capacitor impedance is set to achieve the unity gain bandwidth and, therefore, the product of the capacitor reactance and the transconductance must be unity at the crossover frequency:

Since we have already determined that the transconductance is the reciprocal of the target impedance, we can substitute and set the crossover frequency to be between 1/10th and 1/6th of the switching frequency.

For convenience, the 250kHz setting, which is already in place on the evaluation board, is retained. Based on the desired target impedance of 14mΩ, the total required capacitance is between 270uF and 450uF, and the ESR should be approximately 14mΩ. A single 330uF/15mΩ capacitor (KEMET T520D337M006ATE015) is selected. Solving Eq. 3 for crossover frequency results in a value of approximately 35kHz, which is between 1/10th and 1/6th of the switching frequency.

Power Stage
The total transconductance is the product of the error amplifier gain and the power stage transconductance. The power stage transconductance is often determined based on establishing the current limit. In some implementations, the RDSon of the MOSFET or the DCR of the output inductor is used to sense current, in which case these characteristics define the power stage transconductance.
The power stage transconductance for the LM25116 evaluation board is set for a 10A current limit by the 10mΩ current sense resistor (R11) and the current sense amplifier gain (10). The resulting power stage transconductance is :

This is one of those places where a measurement is beneficial, as these low value current sense resistors aren’t always what they appear to be [1]. Using a 4-wire ohmmeter, the in-circuit resistance of R11 is measured to be approximately 12mΩ, resulting in a reduced power stage transconductance of 8.3. The actual transconductance is verified by measuring the error amplifier output voltage as a function of load current. The resulting measurements, the graph, and the extracted trendline are shown in Figure 3. Note the current limit is a bit shy of 10A due to this increased resistance, but the resistor is retained for convenience as it’s difficult to change.

Figure 3 Measure error amplifier output voltage vs output current as measured on the evaluation board. The curve fit trendline indicates a transconductance of 8.6, close to the value obtained using the 4-wire ohmmeter.

Error Amplifier and Compensation
With the power stage and overall transconductance values determined, the error amplifier gain is determined to be:

The error amplifier associated portion of the evaluation schematic is shown in Figure 4. The complete evaluation design information can be found in [2].

Figure 4 A portion of the evaluation board schematic shows the voltage divider (R3 and R4) which must be adjusted to change the output voltage from 5V to 3.3V. Several other changes are also made.

Several component changes are required to obtain the flat impedance characteristic. Specifically, resistors R3 must be changed in order to adjust the 5V output to approximately 3.37V at 0A to result in 3.3V at the mean current of 5A. Capacitor C6 is shorted using a 0Ω resistor, since we do not want a low frequency recovery, but a flat impedance. C5 may also require modification to cancel the zero created by the output capacitor ESR.

First, R3 is changed from 3.74KΩ to 2.2kΩ resulting in the desired 3.37V output. The error amplifier gain is then set by the ratio of R10 and R3.

Since the installed value is very close at 18kΩ it is retained as is. C5 is selected in order to offset the zero from the output capacitor and ESR with a pole from R3 and C5.

Since the original 100pF capacitor had to be removed, I measured the blank pads where C5 mounts to be 20pF, requiring 236p. A 220pF capacitor is installed.

Output Inductor
Though the output inductor is not a significant contributor to the output impedance, it is important to use an appropriate value. The relationship between the inductance the ripple current is:

The evaluation board includes a 6uH inductor, and, while it could likely be reduced to 4.7uH, it is difficult to replace. So the 6uH inductor is retained.

Emulated current mode control also requires a ramp to be developed in order to reconstruct the slope of the inductor current. This capacitor is shown as C4 in Figure 4.

For the LM25116, the ramp charge current is 5uA, and the value of C4 can be calculated as: The installed value is 220pF, and, while a 240pF could be installed, it is reasonably close and so it is left as is.

The Final Model and Simulations
The final simulation model allows simulation of the control loop stability, small signal AC impedance, and both small and large signal transient response results (see Figure 5).

Figure 5 A simplified state space average model shows the error amplifier stage, power stage transconductance, and output capacitor.

The simulated impedance for the original evaluation board design (blue) and the flat impedance design (red) are shown in Figure 6. The resulting impedance is quite flat at 14mΩ as desired.

Figure 6 impedance simulation of the modified VRM shows very flat response and an excess inductance of 1.8nH. The simple VRM model for simulation purposes is 14mΩ and 1.8nH.

The measured impedance is also quite flat at the desired 14mΩ impedance value. The low frequency level can be fine-tuned using resistor R10, while the slight impedance peak near 60kHz can be fine-tuned using C5. The slight dip at 250kHz is due to the ESR being a bit low. A slightly higher ESR capacitor could be used to improve the flatness in that range. The flatness shown here is adequate for nearly all power distribution network (PDN) applications.

Figure 7 The 2-port impedance measurement result shows a flat response at 14mΩand an inductance of 1.8nH. The inductance is computed from the 112mΩat 10MHz.

The simple L-R model requested by many signal integrity (SI) simulators is therefore 13mΩ and 1.8nH. One method of reducing this inductance is to parallel multiple capacitors. The capacitor inductance is mostly independent of the value of the capacitor and more related to the case size. Paralleling two 150uF 35mΩ capacitors in the same series would reduce the inductance to approximately 1nH while the 100uF 45mΩ capacitors would result in approximately 700pH. Paralleling lower value capacitors is also frequently less expensive, though requiring more PCB area.

Additional decoupling capacitors are generally used to reduce the inductance at the point of use, but this decoupling is not typically part of the VRM.

The 2-port impedance measurement is transformed to the time domain by moving the network analyzer port 1 cable to a 50Ω arbitrary waveform generator (AWG) output, and the analyzer port 2 cable to a 50Ω channel oscilloscope input. The average step response (red) is shown along with the switching ripple (yellow). The squareness confirms the flat impedance profile. The slight rounding at the edges is due to the ESR being a bit low (see Figure 8).

Figure 8 The time domain response is obtained by exchanging the network analyzer for an AWG and an oscilloscope. The average response is shown in red while the ripple is included in the yellow trace

Conclusions
We successfully modified the evaluation board design to yield the desired, flat impedance of 14mΩ. Though it took more than 5 seconds to explain the process, it can easily be automated, using the design requirements as inputs and allowing the remaining terms to be automatically determined within the simulator or using a spreadsheet. The spreadsheet shown in Table 1 computes each parameter, based on the design inputs. Each decision can be overridden. For example, the calculated target impedance is 33mΩ max and this is also entered into the set target impedance which can be overridden.

Table 1 Spreadsheet takes input design parameters in green and calculates the remaining parameters.

The minimum and maximum capacitor bounds are also computed while the final selected value can be chosen and this chosen value is used for the remaining calculations. These overrides are also allowed for other entries, including the PGFS and the output inductance. It is important that these decisions and selections be made in this order.

Note: This spreadsheet will be available and explained as part of the Power Integrity Bootcamp at DesignCon 2016 in January 2016.

More information on registration is available here.

References
[1]https://www.how2power.com/pdf_view.php?url=/newsletters/1207/articles/H2PToday1207_design_Picotest.pdf
[2] https://www.ti.com/lit/ug/snva232a/snva232a.pdf
[3] PCB characteristics affect PDN performance

Also See

    Bouncing short beats clean one for power system testing
    PDN design essentials for wideband low impedance
    PCB characteristics affect PDN performance