Design and verification in a fragmenting world
The European Design and verification conference has celebrated its 10th anniversary and is looking to bring engineers together to face an increasing number of challenges in the semiconductor industry, from AI to multiple languages and more complex system verification.
Nick Flaherty talks to Martin Barnasconi from NXP and Mark Burton from Qualcomm, part of the organising committee of DVcon Europe, about the plans for the next conference in October.
The conference added an academic stream of papers with research alongside papers from industrial users of design and verification technologies.
“We did some experiments in the programme to expand into the academic domains,” Barnasconi tells eeNews Europe. “There are constraints on inviting the academic world but we got good feedback on connecting with industry and blending the two programmes together was appreciated by both industry and the research world”
“We have been talking about it on and off for a decade rather than bolting it on as a sub-conference and there was some concern there,” adds Burton. “The quality of the papers on the mainstream track took a step up. We had a larger selection with more submissions and overall I was impressed. We have been very functional, rating the papers rather than selecting them. Part of the role of the conference is to publish and share best practise and get peek into the process elsewhere.”
The aim is to expand the DVcon Europe conference into adjacent areas to break down the silos of design and verification.
“We are in a setting with the optimal floorplan, and I would rather expand in neighbouring disciplines, to have hardware and talking to software, to systems, so we really try to connect people. The biggest challenge I see in the industry is we are in our own silos but the world is more complex than that,” said Barnasconi.
“In verification we have people who are still in the UVM bubble who are having to deal with system issues, capturing the system intents and the system model so it’s a shift from design verification to system verification from the IP to the SoC level,” he said.
This was reflected in the conference says Burton. “We definitely had more papers from software and one of the biggest feedback items was system design. One of the reasons I think we are doing well on that is that the scope has changed, with people talking about hypervisors which you wouldn’t have seen a few years ago.”
Another of those issues in machine learning and AI which is more about software and system performance..
“We really like to emphasise a use case to improve coverage or the test quality of the model,” said Barnasconi. “It will be interesting to see which user companies or EDA companies come up with practical solutions, one of the practical issues is how engineers can use it, and end users are not really using it as users we want to understand what is happening.”
“There is also an IP issue,” says Burton, with the data used to train the AI frameworks.
As a result formal verification is one area where AI is likely to be adopted faster. “I think formal verification is a different case with static analysis whereas with simulation everything is in flux with different simulation so those techniques find their way into formal quicker,” said Barnasconi.
Rather than an AI revolution, this is driving more diversity for the conference with different languages and different AI techniques.
“The more diversity we can get in people and the topics the better so my hope is that we will be evolutionary with more system level and virtualisation and modelling and simulation, I hope we see more breadth rather than specific issues,” said Burton.
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“What you do see is many different languages for tackling the problems, SystemVerilog, UVM, more and more Python for AI, and this might even help us have more methodology discussions,” said Barnasconi. “If we can exchange more knowledge we can connect communities.”
“In some papers people used a UVM methodology to verify RISC-V processors in SystemC or Python so its about the methodologies rather than code bases being reused,” he said. “If we can encourage that, then that is a way to connect different disciplines, but it is not easy.”
The conference will continue to be global with a European focus, which will naturally include the areas such as Internet of Things (IoT) and automotive. The recent DVcon Europe had keynotes on AI and a European data centre chip, as well as panel sessions on AI and chiplets.
“In terms of coverage and attendance we are addressing the world, with people coming form the US, India and Asia but still we like to give it the local angle with panels and keynotes highlighting the European flavour but for the rest of the programme we are truly global,” said Barnasconi.
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“We need to move from the end product to edge technology and into the cloud and companies making end products are not good at cloud products and the other way around. So we can bring edge and clod software closer to the hardware. I think we need to expand form the physical boundary of the SoC and that is one of the challenges for the coming decade.”
DCvon Europe 2024 will be held at the Holiday Inn in much on 15th and 16th October. Submissions for initial papers close on 22nd April 2024.
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