Alternative approaches can include focusing on the “controlled impedance” of PCB transmission lines and/or using other trace-impedance values.
Let us examine a layer-stack design and see how the PCB trace width affects layer count (cost) and trace impedance (performance). In Figure 1, routing channels of the same width are shown on a signal layer for three PCB transmission lines: a 100-Ω differential pair, a 50-Ω and 60-Ω single-ended.
Figure 1: Routing channels of the same width are shown on a signal layer for three PCB transmission lines for a 100-Ω differential pair, a 50-Ω and 60-Ω single-ended.
The 100-Ω differential-pair is usually determined prior to the single-ended and should be fitted in the routing channel (between the vias) without discontinuities because they are usually for higher speed digital signals. Once the trace width and spacing of the 100-Ω differential-pair have been designed, the trace width for 50-Ω or 60-Ω single-ended on the same layer is usually determined accordingly. Changing the trace width alone for the single-ended traces will lead to different trace impedance. The trace routing yield per channel is:
– Right: One 100-Ω differential-pair with 4mil trace / 5.5mil space.
– Middle: Two 60-Ω traces for single-ended with 4mil trace / 4mil space.
– Left: One 50-Ω trace for single-ended with 6.5mil trace / 7.4mil space.
Note: This example assumes that the minimum trace width and spacing are 4 mils (0.004 in./ 0.1 mm).
In this case, the engineer needs to make trade-off decisions on using either 50-Ω traces, which use up more PCB space and possibly more layers, or 60-Ω traces which use up less PCB space and possibly fewer PCB layers.
next; using reference designs…
Using IC reference designs
The reference designs and recommendations in the documents provided by IC manufacturers are often used as starting points for schematics and PCB layouts in board-level hardware designs.
The techniques adopted for designing high-speed digital interconnects in these documents were most likely re-used in the designs for specific end-products. For example the decision to use a memory interface without termination could have been determined due to the large operating margins of the memory in the reference schematic. However, for cost savings the design engineer may choose alternate devices with different I/O buffer characteristics from those used in the reference design. The engineer would then need to decide if the non-terminated memory interface should remain in the new design.
Reference designs are an essential part of making PCB design decisions. However it is important to have a deep understanding of the principles and limitations behind the techniques being applied in the reference designs. Only then can optimal design trade-off decisions be made.
PCB traces and PCB transmission lines (PCB TL)
When characterising the PCB traces for digital signals in a PCB design, the following should be taken into account:
– Rise-time (tr )/fall-time of the digital driver, and slew-rate-control if any
– Output impedance (Zo), and drive-strength-control of an output buffer if any
– Flight-time in the PCB trace (tpcb)
– Internal terminations for both driver and receiver
– External terminations at both driver and receiver
The table next page shows possible types of PCB traces…
The table below shows possible types of PCB traces interconnecting a digital driver and receiver (referring to Figure 2)
Electrically long (tpcb > 0.2x tr) PCB traces are acting as a PCB transmission line (PCB TL). Electrically short traces (tpcb < 0.2 x tr) are acting as a lumped LC circuit. The impedance-controlled trace (PCB TL) should be specified in a PCB design file to ensure that the PCB is fabricated with the trace impedance within the specified values. The PCB fabricator can also measure the actual trace impedance and generate a report for you upon request.
Flight-time tpcb in the PCB traces is the only parameter associated with PCB layout among the parameters involved in determining whether or not a PCB trace is a PCB transmission line. It is important in a product design team to have consensus that it is the task of both the electrical design engineer and PCB designer to design appropriate type of PCB transmission lines for digital signals.
The table below shows what values the PCB TL impedance should be in order to match the terminations (referring to Figure 2).
Note 1: Wherever possible, Zpcb-TL can be set equal to Zo so that there is no reflection back from driver to receiver.
Note 2: Assuming a high impedance input.
Note 3: Zo = Driver’s Output Impedance, RT = End Termination Resistance, Rs = Source Termination Resistance
Impedance-matched PCB TLs are the best choice for signal integrity (SI) performance because they eliminate signal reflections between the driver and the receiver. However, termination resistors on PCB TLs increase the BOM cost and the power consumption when end-termination (RT) is used. End-termination (RT) is suitable for multi-drop links, and source-termination is a good choice for uni-directional signals, such as clocks. When margins for logic voltage and timing are large enough, non-terminated PCB TLs are often seen in many digital interfaces.
PCB traces will behave differently depending on not only the length of the trace (or flight-time) but also the I/O characteristics of digital driver and receiver and the terminations employed. PCB trace width is a factor in determining both the PCB trace impedance and the yield of trace routing channel – low yield of the routing channel demands high PCB layer count. There should be options for choosing the impedance of PCB transmission lines, and a 50-Ω trace (PCB TL) is not the only choice.
While the IC manufacturer’s reference designs are essential, they should not be considered as the “best practices” for the PCB design of a new product. This is because the process of determining what is “best” is one of making design trade-off decisions that balance performance, cost and manufacturability. It is an important step to characterise the PCB traces for each digital interface presented in a design accordingly in order to optimise the entire PCB design and achieve high signal integrity.
This article was contributed by Nuvation Engineering.
Pi Zhang is Senior Design Engineer and Karl Morant is Lead Design Engineer, at Nuvation Engineering
Howard Johnson, Martin Graham, High Speed Digital Design: A Handbook of Black Magic