Design platform supports hotswap of FPGA components
Xylon in Croatia has launched a framework that allows IP modules to be swapped in and out of an FPGA while in operation.
The Dynamic Function eXchange Design Framework with Isolation Design Flow (logiREF-DFX-IDF) is designed to work with Xylon’s logiVID-ZU-GMSL2 kit. This has an AMD-Xilinx Zynq UltraScale+ MPSoC ZCU102 evaluation board that processes four HD video streams from four Maxim Integrated GMSL2 video interface automotive cameras. Each camera is reconfigurable on the fly with three different filters, on the programmable logic level due to the use of Dynamic Function eXchange (DFX).
The design framework is intended to build upon the existing logiADAK-VDF-ZU design, adding support for new AMD-Xilinx Vitis Unified Software Platform 2021.1 and AMD-Xilinx Vivado Design Suite 2021.1.
DFX is the ability to reconfigure blocks of programmable logic while they are continually operating, with the use of partial bit files. DFX is working in tandem with the used Isolation Design Flow (IDF) methodology, which isolates potential faults to a single region on the chip, to ensure functional safety for safety-critical applications.
Another layer in this drive towards functional safety is the implementation of the AMD-Xilinx Soft Error Mitigation (SEM) IP Core in the design. SEM provides the ability to detect and correct single errors in the configuration memory of the programmable logic, as well as detection of multiple configuration errors, in which case it triggers reconfiguration for the affected isolated chip region. A demo application of error correction is included in the design framework.
The logiREF-DFX-IDF reference design, including the Xylon IP Cores, is available for free evaluation.
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