Design tool automatically generates IP blocks
The software tool will read process design rules, constraints, and detailed system specifications and automatically generate an IP layout block. The primary goal of the technology is to reduce design time as well as the silicon area of circuits.
“The technology is manufacturing process aware to support older and advanced nanometer processes, making it a flexible tool for IC design firms,” said Danny Rittman, CTO of GBT, in a statement. “An automatic IP layout block generator will offer the capability to create the necessary sub-systems at a very short time, enabling much faster and cheaper IC projects designs.”
- Thalia completes 20 analogue IP reuse projects at 22nm
- Perforce buys Methodics to boost IoT chip IP management
No indication was given of how the tool would work or how broadly generic or specialized it would have to be.
Related articles:
- AI startup raises funds to improve chip yields
- RF EDA tools move to the cloud
- AI tool cuts 3nm chip design times
- EDA flow cuts ASIC modelling time from months to days
Other articles on eeNews Europe
