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Designing JESD204B converter systems for low BER, Part 1

Designing JESD204B converter systems for low BER, Part 1

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By eeNews Europe



Many real world sampling systems, such as test and measurement equipment, cannot tolerate a high rate of analogue to digital (ADC) or digital to analogue (DAC) processing errors. These systems essentially require a converter with a low bit error rate (BER). Historically, the conversion error rate of the core converter alone is what has dominated the overall BER. However, with the adoption of the new high speed serial digital interface link, known as JESD204B, between converters and FPGAs, the error rate within the digital transmission line cannot be ignored as a potential contributor to the overall BER.

As a third generation serial interface standard, JESD204B data rates top out at 12.5 Gbps per lane and can span multiple lanes per link, with the next generation of the specification pushing beyond 12.5 Gbps. The speed and quantity of data that is sent per link requires careful attention to several key design criteria in order to minimise the overall BER and prevent the digital data communication from being the dominant error contributor of the converter system.

There are several active and passive elements to the converter JESD204B link that, when considered proactively, can effectively mitigate the digital serial data path as the main contributor to the overall BER. The dielectric material used within the PCB, the inter-symbol interference (ISI) created by the lane layout and the transmission line impedance are all passive elements of the system design that can impact the BER of the link. Conversely, active on-chip transmitter and receiver channel compensation techniques as well as automatic adaptation elements can also substantially improve the BER. Several robust measurement techniques exist to isolate and measure the BER of just the JESD204B link, outside the converter core.

To understand, improve and reduce any impact of the JESD204B link BER on the converter, we answer some common questions from JESD204B system design engineers. Firstly, how is JESD204B link BER determined in the first place?

Determining BER for JESD204B links

ADCs and DACs for instrumentation systems often need to meet a strict error rate standard. The quality of many instrumentation systems can be determined by the error rate occurrence. While a typical conversion error rate can be sought within a converter’s analogue core, the digital data link to the needs to have a better error rate in order to prevent being the dominant contributor. Therefore, not only does the analogue conversion error rate need to be measured, but also the BER of the digital link transmission.

BER in a serial or parallel digital data transmission is the ratio of the number of detected errors at the receiver divided by the total number of bits sampled. BER testing in a digital data stream implements a long pseudo random sequence that is started within a transmitter using a common seed value at both ends of the transmission. The pseudo random pattern should ideally have a long non-repetitive sequence to test as many digital combinations as possible. However, real pseudo random patterns have a repetitive sequence that can change with different seed values. The receiver will also know the seed value of the sequence and have the expectation of an ideal transmission. The BER is precisely calculated by observing the difference in the received data compared to the ideal pattern. Mis-matches in the pseudo random sequence data, based on the seed value, between both ends are counted as bit errors.

Next page; sources of bit-errors…


A bit error in a high speed serial interface such as JESD204B can occur due to one of the following scenarios:

– Timing jitter causing an edge transition to occur inside the sampling region due to conductor loss and dielectric loss attenuating low and high frequency signal components differently.

– Amplitude noise causing an incorrect voltage level Vhigh or Vlow capture due to conductor loss and dielectric loss attenuating low and high frequency signal components differently

In addition to the key analogue performance metrics of an ADC or DAC, key qualitative plots are also used in a converter datasheet to denote the performance of the SERDES link. Some of the most commonly used graphs are the data eye diagram, the ‘bathtub’ curve of error rate vs. unit interval, and a time interval error histogram.

The data eye diagram for the output of an ADC shows the cumulative persistence magnitude of the output signal swing into a defined transmission line load. It is often compared to the mask of a specified ‘keep-out’ area that defines the remainder of the cumulative margin available for the channel loss, inter-symbol interference and receiver clock and data recovery.

Figure 1: A Typical JESD data eye diagram.

A bit error rate plot vs. the unit interval comparison size of the bit stream is commonly referred to as a ‘bathtub curve’. This is because the slope of the plot resembles that of a cross-section of an actual bathtub: an example follows in the online continuation of this article. It defines the available portion of the unit interval (UI) that can reliably be sampled by the receiver in order to achieve a given bit error rate.

As the test pattern length is increased, the higher the potential there is for jitter and other perturbations to decrease the available UI interval for sampling. For any bit error rate, the available timing portion of the unit interval can be established.

Some portion of the curve above the arrow is actually measured, while the remainder below the arrow is extrapolated. The important information to understand from this plot is that the available sample point within the unit interval of a data bit becomes tighter as a lower error rate is required.

Figure 2: A “bathtub” curve shows the available unit interval (UI) for a serial digital receiver’s sampling point in time compared to the expected bit error rate of a link. The curve above the arrow is measured, while the curve below the arrow is extrapolated.

Can the JESD204B link BER be measured mutually exclusive of the normal converter operation?

The JESD204B specification provides a requirement for both a long and short pseudo-random pattern sequence. By disabling the normal converter function and enabling the pseudo-random output pattern as a test mode, the BER between the SERDES transmitter and receiver can be measured. Since the same sequence is known on both ends of the link, the transmitter and the receiver can synchronise to the same starting seed value. A bit-for-bit comparison can be made for the entire length of the sequence. Each SERDES lane BER can be measured independently or as a total link.

A BER confidence level (CL) is an extrapolated expectation of an error in the future, despite not measuring to a certain failure rate. This allows a reduction in the total number of samples taken for a given BER, at the expense of having less than 100% certainty. Measuring to an absolute 100% certainty would mathematically require an infinite duration of samples. Therefore, an industry rule of thumb is that a 95% confidence level is relatively close enough to a known value with a balance between some uncertainty and actual measurement time. If testing were to be repeated one hundred times, we would be able to accurately identify the error rate 95 of those times.

A bit error rate, with an associated confidence level, can be tested with or without errors. For simplicity, let’s consider only the case when no errors are measured. The natural logarithmic relationship for confidence level and sample count can be represented mathematically with the following equation:

where; N = Measured Sample Count; BER = Bit Error Rate; and CL = Confidence Level

For a 95% confidence level with no measured errors, we must take about three times the number of samples as the inverse expected BER. Measuring to a 100% confidence level, where CL=1.0 for any BER value, mathematically takes an infinite amount of samples (N) as –ln(0) → infinity.

N*BER = -ln(1-0.95) = -ln(0.05) = 2.996

Figure 3: This is a measured samples plot of N x BER vs. confidence level. Notice that in order to achieve a 95% confidence level for a bit error rate, N x BER must be nearly 3.

next page; PCB material trade-offs…


What are the tradeoffs of premium dielectric PCB material, trace length and active channel compensation techniques in my system?

The BER of the system can be greatly affected by the quality of the link transmission line. Transmission of high speed data using physical media involves dealing with electrical conductors such as copper in materials such as FR4 or other premium dielectrics. When used within a PCB, they naturally create a network of resistance, capacitance and inductance with materials of different dielectric constants. These physical properties in a PCB define the bandwidth of the transmission line and its characteristic impedance. This will affect the rise and fall times of high speed signals on the board. The physical properties, design and variability of these PCB materials will affect the quality of the transmission line and thus affect the BER of the system.

In a transmission line, the conductor loss and dielectric loss act in two different ways upon the signal transmitted. For low frequency components of the transmitted signal, conductor loss and dielectric loss will attenuate the signal’s highest frequency component. This mechanism in transmission lines produces the effect of a low pass filter; transmission lines on PCBs are low pass filter transfer functions to serial data transitions. The slope of the low pass filter is a function of conductor loss and dielectric loss, and is commonly measured as insertion loss. Therefore, both the length of the transmission line and the quality of the material will impact the insertion loss.

Higher quality PCB materials typically have a lower dielectric constant (Dk) and lower dissipation factor (Df). These both contribute to the reduction in dielectric loss and conductor loss. Dk can improve both dielectric loss and conductor loss, but let’s first discuss conductor loss in transmission lines.

Conductor loss typically increases with a longer conductor. But, another way to increase the conductor loss is by increasing the data rate, due to the skin effect phenomena caused by eddy currents. The skin effect is a known phenomenon where the electrons in a metal conductor are pushed towards the outer surface, thus limiting the area of the conductor where electrons can freely flow. A limitation to the area where electrons can flow means an increase in conductor loss as data rates increases.

Transmission lines in PCBs are usually designed with a target of 50Ω single-ended characteristic impedance, or 100Ω differential impedance. Equation Eq2, below, is the typical equation used for calculating single-ended impedances of microstrip lines. Using the Isola Group 370HR datasheet with relative Dk of εr=4.24, Df of 0.025, for a typical layer 1 to layer 2 height of h=8mils [0.008 in/0.2 mm], 1oz copper (t=1.41mils, or 0.035 mm), and trace width w=13mils (0.33 mm), a characteristic impedance of about 51Ω can be achieved.

If the PCB material is upgraded to Rogers 4003C, using a typical Dk of 3.55, Df of 0.0027 and keeping the typical height of h=8mils, 1oz copper (t=1.41mils), the trace width would need to increase to w=15mils (.038 mm) in order to maintain a characteristic impedance close to 50Ω. An increase in the width of the conductor means an increase in surface area, which directly improves the conductor loss due to skin effect. This will achieve the dual benefits of less dielectric loss and less conductor loss.

Figure 4 has two insertion loss plots. The top shows the insertion loss of 12 in. microstrip transmission lines compared across different types of PCB materials. The lower plot highlights the insertion loss of 370HR PCB material vs. different transmission line lengths. It shows the effects of both dielectric loss with materials of different Dk and conductor loss with different trace lengths. Both contribute to signal attenuation loss at higher frequencies. As expected, higher quality materials having a lower Dk show less loss compared to lower quality materials with higher Dk values. In the same manner, shorter trace lengths show less loss when compared to longer trace lengths for a given PCB material.

Figure 4: Insertion Loss vs. PCB Materials and Trace Lengths, highlighting a higher loss for longer lengths and materials with a higher Dk

next; effect of transmission link quality…


How does the quality of the link transmission line potentially affect the BER of the system?

Since some instrumentation systems require relatively long link lengths from signal acquisition to the processing core within an FPGA or ASIC, the layout of this high speed path should not be neglected. In some cases, multiple connectors, backplanes and cables could be required as part of the link transmission line.

The integrity and physical characteristics of the digital transmission line are critical in affecting the BER of the digital JESD204B link. A perfect transmission line for each JESD204B lane would ideally have a 100Ω differential characteristic impedance. Any deviation from the ideal case causes additional insertion loss or increased return loss.

Both timing jitter, also known as data dependent jitter, and amplitude noise are directly affected by the lossy effects of the transmission line. Specifically, the conductor loss and dielectric loss, as well as reflections created by changes in the characteristic impedance of the channel contribute to the lossy transmission. All of these mechanisms affect the BER of the JESD204B link and therefore the overall BER of the system.

Figure 5: 12.5 Gbps eye diagrams of different PCB materials overlaid against the JESD204B receiver mask

Figure 5 shows eye diagrams profiled against the JESD204B Receiver Eye mask, which are overlays of bit transitions relative to its UI timing reference. The effects of dielectric loss of this 12.5 Gbps PRBS7 signal in 12 in. of channel with different Dk value PCB materials. There is a direct correlation between insertion loss caused by different PCB material (Figure 4 top) and the amount of eye closure relative to the eye mask for a fixed channel length.

For example, Rogers 4003C material has the lowest Dk value and measures the least amount insertion loss for 12 in. of channel length. This produces the best eye opening in Figure 5. Conversely, 370HR material has a higher Dk value. It exhibits a higher insertion loss for 12 in. of channel length, therefore producing the worst eye opening.

About the authors

Ian Beavers is an applications engineer for the High Speed A/D Converters team at Analog Devices Inc., Greensboro, North Carolina. He has worked for the company since 1999. He has more than 18 years of experience in the semiconductor industry. He has a bachelor’s degree in electrical engineering from North Carolina State University and an MBA from the University of North Carolina at Greensboro. He is a member of EngineerZone’s High-Speed ADC Support Community. Feel free to send your questions to IanB on Analog Devices’ EngineerZone Online Technical Support Community.

Jeffrey Ugalde is a Product Engineer High Speed Converters team at Analog Devices, Inc. (Greensboro, North Carolina). He has worked for the company since 2003. Jeffrey has over 11 years of experience in the semiconductor industry. Jeffrey has earned a Bachelor’s degree in Electrical Engineering and Masters of Science in Electronic Engineering from the University of North Carolina at Charlotte. Jeffrey is an EngineerZone user in the JESD204B Support Community. Feel free to send your questions to jugalde on Analog Devices EngineerZone Online Technical Support Community.

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