EFLX is a low-power fully functional FPGA IP that can be integrated into SoCs, MCUs and other ICs. The EFLX arrays are programmed using Verilog or VHDL. The EFLX Compiler takes the output of a synthesis tool such as Synopsys Synplify and handles packing, placement, routing, timing and bitstream generation. When loaded into the array, the bitstream programs it to implement the desired RTL function.

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