Digital control library for analog IP
Analog IP licensor Agile Analog has launched a library of digital cells for circuits required to control analog blocks in mized-signal designs.
The Digital Standard Cell Library (DSCL) is available for implementation in thick-oxide based cells, operating above the core voltage domain, minimizing leakage and allowing easy migration across different process nodes even to FINFET technologies, the company said.
The DSCL IP blocks can be optimised for low power, low leakage, high density or high performance. There are options for channel length and various track heights to provide flexibility for designers. For specific design targets such as low-power designs, there is a special Power Management library. The library can be optimised for other PPA targets. It is also possible to generate models at customised PVT corners.
Agile Analog has developed a way to generate analog IP called Composa. Major foundries are supported including TSMC, GlobalFoundries, Samsung Foundry and SMIC as well as other IC foundries and manufacturers.
“The Agile DSCL has been developed to enable our customers to embed digital functionality within the analog domain. These digital cells will operate within the analog voltage domain which avoids excessive level shifting to the core domain and enables digital control to be tightly coupled to analog IP,” said Barry Paterson, CEO of Agile Analog, in a statement.
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