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Digital library for mixed signal designs

Digital library for mixed signal designs

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By Nick Flaherty



Agile Analog in Cambridge has launched a digital library to use alongside its reusable analog blocks in mixed signal designs.  

The Digital Standard Cell Library (DSCL) provides a comprehensive library of digital cells enabling designers to implement the digital circuits required to control the analog blocks.

The library is available in thick-oxide based cells, operating above the core voltage domain, minimizing leakage and allowing easy migration across different process nodes even in Finfet technologies.

All the major foundries are supported including TSMC, GlobalFoundries, Samsung Foundry and SMIC as well as other IC foundries and manufacturers.

“The Agile DSCL has been developed to enable our customers to embed digital functionality within the analog domain,” said Barry Paterson, new CEO at Agile Analog. “These digital cells will operate within the analog voltage domain which avoids excessive level shifting to the core domain and enables digital control to be tightly coupled to analog IP. The DSCL has been developed to be process agnostic and therefore is available in the same processes as our analog IP. The library fully supports industry standard digital design methodologies by making all required views available. Our Analog Digital Cell Library is already being used successfully in customer designs to support low power, always-on solutions for applications such as IoT.”

The DSCL IP blocks can be optimised for low-power, ultra-low leakage, high density or high-speed applications. There are options for channel length and various track heights to provide flexibility for designers. For specific design targets such as low-power designs, there is a special Power Management library.

It is also possible to generate models at customised PVT corners.

Agile Analog has developed techniques to automatically generate analog IP to exactly meet the customer’s specifications and process technology. The Composa library uses fully validated analog IP circuits to emulate the design model of digital IP.  

www.agileanalog.com

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