The Cadence VIP for DisplayPort 2.0 enables designers to quickly and thoroughly complete the functional verification of their mobile, Audio-Visual and AR/VR system-on-chip (SoC) designs with less effort and greater assurance that the design will operate as expected. The IP includes a configurable bus functional model (BFM), a protocol monitor and a library of integrated protocol checks to optimize verification predictability. Additionally, the VIP has been designed for easy integration into testbenches at IP, SoC and system levels, helping engineers reduce time to first test and accelerate verification closure. The VIP for DisplayPort 2.0 is part of the broader Cadence Verification Suite and is optimized for Xcelium Parallel Logic Simulation, along with supported third-party simulators.
Cadence – www.cadence.com