Divide by N for synchronizing DC/DC converter clocks

Technology News | April 28, 2014

By eeNews Europe

Automotive power conversion solutions frequently use a step-down dc/dc converter connected to the vehicle battery, switching at a frequency below the Radio MW band (i.e. < 530kHz), plus downstream dc/dc converters (e.g. a power management IC, PMIC) switching above the MW band [1] (i.e. > 1.7MHz). It can be desirable to synchronize their clock frequencies, to make the emissions spectrum predictable during test and production. Synchronizing clocks to a central clock source can also prevent them interfering with sensitive analogue or digital sections of the overall system. Alternatively, multiple dc/dc converters can be all powered off the vehicle battery, each one switching below the MW band. To reduce the MW band harmonics, then synchronizing their clocks out-of-phase can be desirable.

First Application – Single dc/dc plus PMIC
In the first automotive application, Figure 1, the PMIC outputs its own self-generated switching frequency clock of 2.2MHz (above the MW band) and this is to be divided down to clock the TPS54360-Q1 at a frequency below the MW Band. Dividing by four gives 550kHz, which is within the MW band. Dividing by eight (the next power of two) would give a low switching frequency of 275kHz. Dividing by five gives a frequency of 440kHz, just below the MW band. The goal is to use as high a switching frequency as possible to minimize passives’ sizes (the inductor’s size is inversely proportional to switching frequency), whilst placing the fundamental below the MW Band. Dividing a clock by non-powers of two requires a bit more thought. In this particular application the solution needs to be low cost, robust and the ICs automotive-qualified. There is no requirement for the clock to have a 1:1 mark-to-space ratio, which simplifies the solution.

Figure 1 – Two dc/dc Converters with Clock Synchronization at Different Frequencies via a Divide by Five. TPS54360-Q1 is switching below the MW band and the PMIC above it

The Clock Divider
Using a decade counter like CD74HC4017 and feeding back one of its outputs to the reset pin might seem one way to do it, but this will mean that the reset is an undesirable narrow (or “runt”) pulse that lasts only as long as it takes for the flip-flop producing it to reset its own output. The better solution shown in Figure 2 is to use a shift register SN74AHC595 and a logic inverter SN74AHC1G04, which are both also available as automotive-qualified ICs, SN74AHC595-Q1 and SN74AHC1G04-Q1. For High Reliability applications, an SN74LV595A-EP and inverter SN74LVC1G14-EP can be used instead. For space-rated applications, the slower SN54HC595-SP and inverter SN54HC04-SP (or other) can be used. Examining the datasheet shows that each of the shift register’s outputs is double-buffered, in the sense that two flip-flops are cascaded per output. The reset that is generated by the output of the second of the flip-flops in the double-buffer is only resetting the first flip-flop in it and therefore it lasts one full clock cycle.

Figure 2 – A Divide by Five Clock Circuit, Showing its Four Outputs. The 10k pull-down is for when OE/ is high

Figure 3 – Divide by Five Waveforms. The rising edges mark the 0, 20, 40 and 60% phases that can be used to synchronize the converters

The waveforms are shown in Figure 3 and show that a divide by five clock output is available in four places, each with a different mark-to-space ratio and having different phases. The term “phases” here refers to the rising edges of the outputs, which occur at different points in time and are used to synchronize the dc/dc converters. The term “mark-to-space ratio” is the ratio of the time the signal is high divided by the time it is low. You can opt to use whichever output is most useful for your application. In this application, the TPS54360-Q1 RT/CLK input is falling-edge triggered and any of the Q outputs can be used, once they have been inverted. Note that in applications where the input voltage is doubled such as is the case for a lorry running off a 24V battery or other 24V industrial applications, then a divide by six could have been constructed using the solution in Figure 3, but moving the reset from QC to QD. (When the input voltage to the dc/dc converter is doubled and if the switching frequency remains the same, then the on-time is halved. Dividing by six reduces the switching frequency and increases the on-time to keep it above the minimum on-time of the IC.)

Figure 4 – Cascaded SN74AHC595 for a Larger Divide by N Ratio e.g. N=17

Using one SN74AHC595 gives the possibility to divide in the range of three to ten by changing which Q output is used to make the feedback reset signal. Using the QH’ output from the IC and feeding that into the SER input of a second allows for expansion, up to a divide by eighteen. Additional stages can be cascaded. Figure 4 shows an example for a divide by seventeen. Seventeen outputs produce the same clock frequency, but with different mark-to-space ratios and phases, given by the equations below.

For a divide by N, then each output (up until the output that is fed back to form the reset) has a divide by N clock on it, but with a different mark-to-space ratio of 1:(N-1), 2:(N-2), …… (N-1):1. E.g. for a divide by N=5, then the four available outputs have 1:4, 2:3, 3:2 and 4:1 mark-to-space ratios.

Each output also has a different phase (rising edge) of 100% x [0, 1/N, 2/N, …… (N-2)/N]. E.g. for a divide by N=10, then the nine outputs have 0, 10, 20, 30 ….. 80% phases.

The longest delay in Figure 2 is from Clk Input-to- QC -> inverter Tpd -> SRCLR-to-QH’ -> D input set up time. Summing the max delays over temperature in the datasheets of the commercial or automotive versions of the ICs gives a limit on the Clk Input of 20MHz when powered off 3V3, or 30MHz when powered off 5V.

The advantages of this clock divider are:

It is clock-synchronous – there are no glitches or race conditions. Each D-type flip-flop output of the internal shift register is buffered by a further D-type flip-flop, which means the reset SRCLR/ pulse is not a glitch, but one full clock period.

The SN74AHC595 has an outputs-enable (OE/) pin that can be used to tri-state its outputs. OE/ could be used during power-up, to wait until the SN74AHC595 is being clocked before allowing its outputs to be enabled to drive the clock-sync pin(s) of the dc/dc converter(s).

There are outputs available with different phases (the rising edges) and different mark-to-space ratios.

By moving the position of the output used to the reset the IC, different divide by N clock outputs can be achieved in the range of three to ten with one IC, or three to eighteen with two cascaded.

The availability of similar or the same parts with different ratings means it can be used in a wide variety of applications.

Second Application – Multiple dc/dc Converters connected to Vbat
A second potential automotive application of the clock divider is shown in Figure 5. Four dc/dc converters are each supplied by the battery voltage, Vbat. In this application, two 3V3 outputs were required, as one of them had to be a for an independently-supplied safety micro-controller. An input clock of 4.75MHz is divided by ten and provides nine 475kHz clock outputs, each with a different phase. (If the available input clock has a higher frequency, then the cascaded approach shown in Figure 4 can be used, as long as a minimum typical RT/CLK pin pulse width of > 40ns is used to synchronize the TPS57140-Q1.) Four of the clock outputs are chosen to synchronize the switching frequencies of the four step-down dc/dc converters. The IC is synchronized to a falling edge input on its RT/CLK pin, so it is necessary to invert the clock divider outputs. The goal was to position the input current pulses so that they fill the available time period and overlap somewhat, so as to try and make the total summed input current as continuous (dc) as possible. Synchronizing multiple converters with a phase shift to each other also reduces the ac current flowing in the input capacitors [2]. The dc/dc converters are all TPS57140-Q1 (1.5A). Other ICs in this family include TPS54240-Q1 (2.5A) and TPS57040-Q1 (0.5A), plus their 60V equivalents. Similar, although not the same, are the new TPS54340-Q1 and TPS54540-Q1 higher-current devices, plus their 60V equivalents.

Figure 5 – Interleaving four dc/dc converters using four 475kHz clocks with phases of 0, 40, 60, 80%. The input current pulses for each converter are also shown over one switching period. Two of them are drawn as negative pulses for the sake of clarity, but in reality all are positive currents.

Note the use of tri-state inverting buffers to drive the RT / CLK pins of three of the dc/dc converters, because the RT / CLK input responds to a negative-going edge. The 80% clock output on QH does not need inverting because we are using its falling edge.

The switching frequency (fundamental) of each converter is 475kHz. This is below the MW band, which spans an approximate 530kHz to 1.7MHz range. However, the 2nd and 3rd harmonics (950kHz and 1.425MHz) lie within it. The fourth harmonic (1.9MHz) lies above it, but is included in the results for completeness. The unfiltered input current of a step-down converter is comprised of discontinuous pulses of currents with high harmonic content. The purpose of the interleaving of the converters is to reduce the magnitude of the 2nd and 3rd harmonics, so as to make meeting the automotive conducted emissions easier, and / or to enable a lower cost input filter.

One way to interleave four dc/dc converters that is commonly seen, is to offset each one’s phase in 25% steps, i.e. 0, 25, 50, 75%. This method is often used when the four individual converters are operating as part of a multi-phase converter. Multi-phasing of dc/dc converters is where their outputs are paralleled to drive a common load and each converter delivers an equal share of the load current. However, in the application under discussion in this article, the output voltages and currents are different / independent. Therefore an alternative method of interleaving was also tried, by offsetting the phases in 0, 40, 60, 80% steps. The phased synchronization of the input current pulses of the four dc/dc converters is shown in Figure 5.

The two different methods of interleaving of four converters was also contrasted with another valid approach, which uses only one dc/dc converter connected to the vehicle battery and processes all the power to give one 5V output at 10W, as in Figure 1. All three methods were simulated using Texas Instruments powerful, free simulator, TINA-TI. In the case of the interleaved converters, the total input current is found by summing the individual converters’ input currents to give the overall input current drawn from the battery, Figure 6. The Fourier Series was computed to yield the rms magnitudes of the input current harmonics.

Figure 6 – Input Currents for Vin=12V. A rise / fall time of 10ns is used.
I1 – input current for method 1 – all power processed through one dc/dc converter with 5Vout.

I2 – input current for method2 – four dc/dc converters interleaved using 0, 25, 50, 75% phasing.

I3 – input current for method3 – four dc/dc converters interleaved using 0, 40, 60, 80% phasing.

Figure 7 shows the table of results computed for the 2nd, 3rd and 4th harmonics’ rms magnitudes for three methods: (1) one dc/dc converter is used, processing all the power to give a 5Voutput at 10W (2) four converters are interleaved with phases 0, 25, 50, 75% and a total of 10W output (3) four converters are interleaved, Figure 5, to maximize the spread of the currents throughout the period, which meant using phases of 0, 40, 60, 80%. Total output power is also 10W.

Figure 7 – RMS Magnitudes in mA of the fundamental (475kHz) and 2nd, 3rd and 4th harmonics. The largest harmonic for each of the three methods is shown in red.

The input voltage and therefore duty cycle, D, of a dc/dc converter connected to the battery changes and so three voltages were tested; 8, 12 and 18V. It was found that the third method of interleaving gave the lowest magnitude of the 2nd and 3rd harmonics, reducing the MW band filtering requirement and consequently its cost/size. Compared to the first method, it shows a > 6dB reduction in the prominent 2nd harmonic across the Vin range. Additional Vin input voltages were simulated (8, 9, 10, 11V) for the third method to check it still produced the lowest 2nd and 3rd harmonics, which it did.

Computing the Fourier coefficients by hand for the first method shows that the largest harmonic is the 2nd harmonic and it is expected to be at its peak when the duty cycle of the dc/dc converter is either 0.25 or 0.75. This corresponds to the largest harmonic in Figure 7, occurring when Vin=18V, because the duty cycle is D = 5/18 = 0.28, which is close to one of the peaks of D = 0.25.

Conclusions
The clock divider allows for division by an integer and can be used in many applications. Two automotive application examples have been discussed where a simple clock divider can be used to synchronize the switching frequencies of dc/dc converters. In the case of the second application, it allows the synchronization phases to be selected to reduce the magnitude of the harmonics falling within the MW band.

References
1. Dan Tooth, Texas Instruments. “Tradeoffs when Selecting Automotive dc/dc Converters.” Bodo’s Power Systems, www.bodospower.com, November 2013
2. Bryan James Smith. “Input Ripple-Current Balancing by Phase Shifting Multiple Outputs.” Electronic Design, May 2013