Dresden firm takes FDSOI down to 0.4V

Dresden firm takes FDSOI down to 0.4V

Technology News |
By Peter Clarke

The IP is available through makeChip, Racyics’ hosted design service platform targeted at startups, small companies, research institutes and universities.

Racyics has executed power-performance-area (PPA) studies for both Cortex and RISC-V based microcontrollers (MCUs) operating at supply voltages down to 0.4V on 22FDX and in Decmeber 2017 it taped out a Cortex-based test chip for silicon validation of its adaptive body bias (ABB) design approach and to show the potential for MCU implementations.

“The 22FDX design flow and IP used for this test chip implemented by us is available at makeChip,” Holger Eisenreich, co-founder and CEO of Racyics, told eeNews Europe in an email exchange. “We are currently developing SoC template designs, which we plan to provide to makeChip customers as an ultra-low voltage (ULV), ABB reference implementation or as base for their own customized ULV SoC.”

Holger Eisenreich, CEO of Racyics

Eisenreich added that the SRAM arrays operate from dual voltage rails based on the Globalfoundries bit-cell kit with the periphery of SRAM operating at 0.4V and the bit cell array using a supply of 0.72V. SRAMs are typically the circuit type that is least able to scale with voltage.

Racyics has developed its own circuits for monitoring of process, voltage and temperature (PVT) that are already silicon-proven in 22FDX. “This is essential for our ABB platform, because the characteristics of the monitors are one input for the ULV library characterisation. Different back bias voltages are used for the different corner characterizations. These voltages are determined by a virtual ABB regulation. This is a new patent pending approach, enabling an ABB aware implementation and sign-off, leading to much better PPA results.”

Eisenreich continued: “From our point of view, Implementation of ULP IoT-like designs at less than 0.5V are only possible based on an ABB scheme. Our ABB approach is even beneficial at 0.8V, resulting in 20 percent more performance in the worst delay corner while having at the same time 25 percent less leakage in the best delay corner. This equals almost another halve node shrink.”

Next: What non-volatile memory?

The MCU test chip is being made without non-volatile memory but from April 2018, MRAM will be available for 22FDX multi-project wafer runs and product tape outs in the form of the third-party IP provided by Everspin Technologies (see Globalfoundries offers embedded MRAM on 22nm FDSOI).

Eisenreich said the company will consider MRAM and other non-volatile memory options, such as phase-change memory (PCM) resistive RAM and ferroelectric RAM as the IP becomes available but would not develop that IP itself. “FeRAM looks promising. We implemented FeRAM testchips in 28nm for local partners NamLab/FMC. As soon as this kind of IP is production-ready for 22FDX we will try to make it available through makeChip,” he said (see Ferroelectric memory startup aims at GloFo’s 22FDX).

Racyics  was founded in 2009 as a spin-off from TU Dresden as an SoC design service provider with focus on advanced nodes. Racyics delivers analog, digital and mixed-signal design services and since 2013 has been a Globalfoundries’ channel partner for EMEA.

“The makeChip idea was born out of academic background. We know quite well, how hard it is to realize complex ASICs/SoCs as an academic group. The idea was to ease this a bit by creating a professional turn-key playground and providing expert support for critical implementation tasks. In the frame of a hosted design environment this is much more efficient than with the traditional Europractice way,” said Eisenreich. “Of course we are also hoping that some of the academic ideas get commercialized by startups that could be our future service and IP customers,” he said.

Eisenreich said that although the hosted design service makeChip is still at the pilot stage it has 25 users, 5 active design projects and is profitable.

Related links and articles:

News articles:

Startup tapes out MRAM-based MCU

Ferroelectric memory startup aims at GloFo’s 22FDX

Globalfoundries offers embedded MRAM on 22nm FDSOI

Dream Chip shows ADAS processor on FDSOI

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