Dual clock 32bit PCI Bus target interface IP core
The core’s main feature is the presence of two clock domains, for flexibility and higher performance; its user-friendly back-end interface can be very easily and effectively tailored to the design needs. The Core supports up to six base address registers and expansion ROM address register with both I/O and memory space decoding from 16 Bytes up to 4 GB. Another important feature is a cache wrapping hardware support and a cacheline pre-fetching capability. The DTPCI32DC accepts size cache lines which are powered from 2 up to 128. It enables also target-disconnect with data, without data or by a target abort. The core is capable of working at 66 MHz clock frequency in the most popular technologies. It assures the PCI timing requirements, as well as other parameters such as FIFO depths number or base address registers which can be configured at the pre-synthesis stage.
Features include:
- Fully supports PCI specification 3.0 protocol;
- Stable clock domain crossing regardless of the clock frequencies;
- Cache wrapping (cache lines must be powers of 2);
- User controlled burst data transfer;
- Possible no-wait state transactions;
- Automatic handling of configuration space read/write access;
- Parity generation and parity error detection;
- Single interrupt support;
- Configurable FIFOs depth;
- Supported backend initiated burst termination (with and without data);
- No tri-state buffers.
DCD; https://dcd.pl/ipcore/1112/dtpci32dc/ and www.dcd.pl
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