DVCon Europe 2015 announces Technical Program

DVCon Europe 2015 announces Technical Program

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By eeNews Europe

Sponsored by Accellera Systems Initiative, DVCon Europe brings chip architects, design and verification engineers, and IP integrators the latest methodologies, techniques, applications and demonstrations for the practical use of EDA solutions for electronic design.

The content in the Technical program for this year’s event has now been published. Chairman of the Steering Committee, Martin Barnasconi (NXP Semiconductors) set the objective of addressing design and verification across the product design value chain; his aim in compiling the program has been to attract, and provide information for, engineers working across a broad spread of companies, and in many different roles within those companies.

That said, he identifies a number of key themes that have informed the 2015 program; in the Automotive arena, issues of safety and security; the trend towards self-driving vehicles, and their functional safety (the subject of a panel session). In the Semiconductor space, the program has a focus on another sector that is strong in Europe – mixed-signal IC design. It has long been the case that design and verification in this space has been more fragmented than in the logic domain, and a theme of the Conference program is how AMS (analogue/mixed-signal) design and verification can be made more coherent.

Attention also turns to the need to bring AMS verification and systems design/verification closer together. Added to that, is the general trend to low power in all forms of design.

Barnasconi notes that in the first running of DVCon Europe, the training content was a well-received component; accordingly, there will be extensive tutorial and seminar content, as well as conference papers; plus the opportunity for verification professionals to meet and, “look over the fence” at what others are doing.

A key element of what the organising committee have been seeking to achieve, is a focus on new methods, reflecting the interests and ambitions of sponsor Accellera. There is, as Barnasconi observes, still no consensus on the “best” design flow and although ESL (system-level design methodologies have been around from many years, there is still great diversity in the use of (for example) SystemC, and System Verilog – and of UVM (Universal Verification Methodology). In fact, the education and training track of the event commences with a tutorial on the use of UVM, and a subsequent tutorial looks at the bringing together of System C and UVM.

Although the concept of UVM is not (now) new, this (the DVCon Europe organisers feel) may be the time it is finding new support; there is an opportunity, Barnascoi says, to bring new verification engineers up to speed on the approach, in less time.

Chairman of the Technical Program Committee, Matthias Bauer (Infineon Technologies) reaffirms the emphasis on the system-level view in the make-up of the conference program. He has sought content around requirements, and verification/validation at an early stage in the design cycle. As the software content of systems increases, the probability of failure rises, and the need grows for a system-wide verification strategy. Alongside papers with this theme, there is also content on fault simulation – and on the need for standardisation, both to reduce the effort involved and to start to harmonise the (many) languages now in use. At the “top end” of this view, there is a paper looking at methods of architectural exploration, that asks how effective current approaches are.

Selecting just three of a complete program of tutorial content gives a further flavour of the event;

Tutorial; UVM Goes Universal – Introducing UVM in SystemC

Tutorial/Panel; The Functional Verification Roadmap: Where Will We Be in Five Years?

Tutorial; The How To’s of Advanced Mixed Signal Verification

Overall, the program offers;

· 15 tutorials moderated by user companies, tool providers and training partners

· Technical program that will comprise 36 papers

· Multiple tracks presenting 26 papers and a poster session hosting 10 posters

· Exhibition with demonstrations from training partners, design tool and IP service providers

· Gala Dinner included as part of the conference

DVCon Europe 2015 takes place on Wednesday November 11th and Thursday November 12th, 2015, at the Holiday Inn Munich City Centre, Hochstrasse 3, 81669 Munich, Germany. There are special hotel rates for conference attendees.

Find DVCon Europe at; – the complete event Conference program and Exhibition Guide is at;

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