DVcon Europe looks to open source EDA challenges
Over 300 of Europe’s leading semiconductor engineers came together in Munich last week for the DVcon Europe conference.
The annual DVCon Europe conference, now in its tenth year, saw a record 58 papers on semiconductor verification and for the first time included a track for papers from researchers as well as industry.
Keynotes covered the latest Rhea1 AI accelerator chip being developed by SiPearl, as well as the impact of AI, with panel discussions on AI and chiplets.
- EDA standards for AI, China
- Nvidia triples Q3 sales, confirms chip leadership
- Working group proposed for federated simulation
The most popular papers at the DVcon Europe conference covered open source EDA tools and asymmetric aging of transistors in clock trees that hits the long term reliability of chips.
Engineers from Bristol highlighted the extreme cost of a failed tape-out that rightly demands high levels of assurance from verification and physical analysis. Companies tend to develop layers of internal tooling and processes around the major EDA vendors’ offerings to help reduce these risks. However, this raises a question of if there is a missing piece of the puzzle say the engineers from VyperCore and PQshield.
They point to GCC and LLVM as two open source compiler suites dominate the industry for C and C++ compilation with support from Apple, Qualcomm, Google and Intel, and that this doesn’t exist in EDA.
“Any engineer involved in design flow development will be familiar with the challenges of tool integration and data management – problems for which little standardised tooling or methodology exists,” said Ben Marshall and Peter Birch.
“In our experience this has led to companies developing vast webs of bespoke shell, Makefile, Perl, and Python scripts that are jealously guarded, often by teams who just want to get on with the hardware design task and don’t have the time to make the most considered decisions. These scripts become critical to the success of each tapeout or delivery, and yet are often been borne out of urgency without deep consideration for their structure or extensibility. It is surprising that, unlike other industry wide problems such as testbench design, there isn’t an agreed approach.”
“Our main desires are that interfaces are standardised, file formats are vendor agnostic and well documented, and the relationship between inputs and outputs of any tool are strongly defined,” they said.
A tool called BlockWork is a free and open source build system built to tackle the complexity of designing, verifying, and implementing a modern ASIC comprising many different components. While extremely flexible, the tool also offers a recommended methodology on structuring a hardware repository and its flow.
“We strongly believe that relaxing NDAs between vendors and customers to an extent that allows tool integrations to be shared would be beneficial to all parties involved, and is the foundation for establishing common practices and tooling for design flows. We offer Blockwork as a stepping stone on this road. We believe that it is built on a solid foundation and will develop over time into a robust and capable build system for even the most complex hardware projects.”
- Report urges boost to Europe’s open source silicon
- Open-source startup offers chip design platform
- $30m for open source end-to-end FPGA software
In the first research track at DVcon Europe, a team from the Israel Institute of Technology looked at how asymmetric transistor aging affects clock trees and the reliability of chips over time and suggested a new design flow.
Reliability is critical for integrated circuits (ICs) to ensure accurate operation over their lifetimes. Transistor aging depends mainly on the bias-temperature instability (BTI) that severely affects reliability, degrading performance and causing critical circuit failures due to timing violations. Asymmetric aging occurs when the degradation is unevenly distributed, intensifying timing violations and reliability concerns.
The team looked at how asymmetric transistor aging affects clock tree design and highlights the role of useful skew, clock gates, and asymmetry between clock buffer delays and net delays in amplifying reliability concerns. They also proposed new design flow guidelines to address asymmetric-aging-related violations.
The call for papers for both industry and research for DVcon Europe 2024 will be issued in early 2024 with the conference taking place on 15th and 16th October.
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