E.U. tackles III-V on CMOS
The ultimate aim is to meet the specifications of future 5G and radar systems aiming for wider bandwidth and higher-resolution images, respectively. Besides IBM (Switzerland), the program will be conducted by Fraunhofer IAF (Germany), LETI (France), Lund University (Sweden), University of Glasgow (UK) and the Tyndall National Institute (Ireland).
using IBM’s template-assisted selective epitaxy–silicon is colored in green, and the III-V semiconductor in red.
(Source: IBM, used its permission)
There will be two phases to the program led by IBM and Lund University, with IBM concentrating on prototyping conventional planar transistors with III-V channels, whereas Lund University will investigate the feasibility of vertical III-V transistor channels.
“First the partners will decide together whether the horizontal or vertical transistor prototypes are the most promising,” IBM scientist Lukas Czornomaz told EE Times in an exclusive interview. “Then we will work together to deliver an RF [radio frequency] test circuit, such as a PA [power amplifier] by the end of the three-year program.”
IBM is confident that its planar method will work, because it has already demonstrated its feasibility at below 14 nanometer in a paper last year titled IBM Scientists Present III-V Epitaxy and Integration to Go Below 14nm.
The way IBM’s process works is by what they call “template-assisted selective epitaxy.” They grow an oxide wire where they want the III-V transistor channel to eventually be for a gate-first CMOS-compatible III-V FinFETs on silicon substrates. Next they coat the nanowire with the III-V material so that it only touches the substrate in just a nanoscale or even angstrom-scale area. Lastly, they removed the oxide from inside the III-V coated nanowire, thus resulting in a III-V nanotube transistor channel in precisely the correct position.
(Source: IBM, used by permission.)
IBM predicts millimeter-wave RF performance at a much lower power consumption level than today, facilitating not just 5G but also cognitive computers, next-generation Internet of Thing (IoT) and the cloud-based platforms supporting them.
Insight’s stated goals are to scale CMOS beyond the seven-nanometer node thereby opening up a whole new range of applications serviced by ultra-high-performance systems on chip (SoCs). The other partners, Fraunhofer, Fraunhofe, LETI, Lund University, University of Glasgow and the Tyndall National Institute also all have III-V on CMOS expertise which they will bring to bear on the project.
Insight is funded under the E.U.’s Horizon 2020 Program for Research and Development (grant number 688784).
— R. Colin Johnson, Advanced Technology Editor, EE Times
Related articles:
Samsung Funds III-V FinFETs in US Lab
Leti brings silicon capabilities to III-V Lab
Researchers integrate silicon, III-V
III-V FinFETs on 300mm silicon wafers at imec
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