A German consortium is working on a €16m project to secure the supply chain for chiplets and boost final assembly in Europe. This is set to create new standards for chiplet assembly with secure elements and an end-to-end design flow.
The T4T project for ‘Distributed Manufacturing for Novel and Trustworthy Electronics’ includes leading manufacturers such as Bosch, X-Fab, Audi and Osram as well as researchers from various Fraunhofer Institutes.
The secure supply of electronic components is of growing strategic importance for Germany, as the relocation of chip making to non-European regions increases the vulnerability to the introduction of malware and espionage functions.
At the same time, the risk of intellectual property (IP) theft of circuit designs by third parties is also increasing, say researchers. So the project aims to add secure elements to chips and chiplets made in foundries in Asia with post-quantum encryption with assembly and encoding of the systems taking place in a trusted environment in Germany.
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The project is looking at two approaches: wafer-on-wafer assembly, and the assembly of chplets on an interposer substrate.
This will lead to standardization of processes in packaging and interconnection technology and define new design specifications and tolerance rules for offset and structure sizes.
Demonstrators by March 2025 will show new design flows and methods and adapted manufacturing processes and will include NanoWired, Suess, DISCO and IHP as well as the Fraunhofer Institutes IZM-ASSID, IPMS, IIS/EAS and the Technical University of Dresden.
The Fraunhofer Institute for Photonic Microsystems IPMS is looking at the interface between classical front-end wafer fabrication and back-end packaging to minimise contamination and defect density and boost process quality. It will also look at how post-quantum cryptography techniques using non-volatile memories (NVMs) will be investigated and tested. This security element, together with distributed manufacturing, should provide additional protection.
The Fraunhofer Institute for Reliability and Microintegration IZM and its All Silicon System Integration Dresden (ASSID) are involved in the production of a 300mm wafer to wafer demonstrator with an encrypted memory element as well as an interposer wafer with integrated chiplets.
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Wafer-to-wafer bonding allows the distribution of functions on smaller chips of a similar size, and provides the basis for a packaging technology adapted to subassembly. UK AI chip designer Graphcore for example is planning to use this technique to combine its chips to get higher performance.
However, the use of different chip sizes in split manufacturing can lead to problems in packaging.
This leads to chiplet assembly, with multiple devices of different sizes on an interposer, or 2.5D assembly
As a result Fraunhofer IZM-ASSID is developing an approach based on the die-to-wafer bonding process and high-density interconnects that enables the combination of different chip sizes on one. The resulting heterogeneous system is expected to contribute significantly to the establishment of new standards for interposers with bonded chiplets that can be used in many different systems.
The Fraunhofer Institute for Integrated Circuits IIS, with its Adaptive Systems Development (EAS) division, will work on an end-to-end design methodology. Components and interfaces required for the design flow will be developed, and the necessary chip and package data will be made available in a modular multi-process design kit.
It will also work on the electrical design of the demonstrators as well as in the electrical measurement following manufacturing.
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