€240m DARE project for AI RISC-V chiplets
Europe’s high performance computing (HPC) joint undertaking has launched a €240m project to develop RISC-V chiplets and software for AI.
The Digital Autonomy with RISC-V in Europe (DARE) project is the first phase of an initiative to strengthen Europe’s technological sovereignty in High-Performance Computing (HPC) and Artificial Intelligence (AI).
The initiative is a direct response to Europe’s strategic need for digital sovereignty, ensuring that the continent has full control over its critical computing infrastructure.
“Europe has long been dependent on non-European HW and SW solutions for its supercomputing infrastructure. This reliance poses risks to security, economic stability, and technological competitiveness. DARE seeks to reverse this trend by leveraging the open RISC-V ecosystem, and the latest chiplet technology, thereby creating truly European products that will power Europe’s future supercomputers,” said the project.
The project hints that the chiplets could be made at project partner imec in Belgium on a leading edge CMOS process using its pilot line. “DARE is daring to start from the top of the technological complexity pile and produce European-designed processor chips for supercomputers, paving the way for Europe’s digital sovereignty,” said Osman Unsal, DARE Principal Investigator at the Barcelona Supercomputer Centre (BSC) which is leading the project.
Dare is coordinated by the Barcelona Supercomputing Centre (BSC-CNS) with 38 leading partners from across Europe to develop next-generation European processors and computing systems, including an optimized software ecosystem, designed for research and industry applications.
Partners include Codasip in Germany, Axelera in the Netherlands and Openchip in Spain developing chips for the first phase over the next three years to build a fully European supercomputing hardware (HW)/software (SW) stack for HPC and AI.
Openchip is developing a vector accelerator (VEC) for high-precision HPC and emerging applications in the HPC-AI convergence domain, while Axelera AI is developing the AI Processing Unit (AIPU) for inference acceleration and the general-purpose processor (GPP) will come from Codasip.
“The launch of the DARE project marks a significant milestone for European digital sovereignty. This ambitious initiative will drive innovation in both hardware and software technologies and leverage the full power of HPC and AI to develop secure, efficient, and European-led solutions for the future,” said Anders Jensen, EuroHPC JU Executive Director.
DARE is using a HW/SW co-design approach, using a carefully selected set of European HPC and AI applications to guide development. A complete SW stack, optimized for the chiplets, will be built in parallel with HW design, using emulation and simulation.
imec and the Julich Supercomputing Centre (JSC) are technical leads, while BSC will also lead the roadmap development as well as the VEC pathfinding efforts while participating in HW and SW development activities.
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