€270m for RISC-V chiplets to build European exascale supercomputers
EuroHPC is to issue call next month for RISC-V chiplet projects in January with €270m of backing.
A Framework Partnership Agreement (FPA) aims to set up a long term partnership between the EuroHPC joint undertaking and a consortium of industry, research organisations and the institutions in High Performance Computing. This would drive a ‘strategic and ambitious R&D initiative contributing to the development of innovative HPC hardware and software technology based on the open RISC-V ecosystem’.
This will be followed by a plan to build and deploy exascale and post-exascale supercomputers based on the technology.
- €8m project for Europe’s first RISC-V supercomputer chip
- European processor project shows shift to RISC-V
- European supercomputer project receives RISC-V test chips
To avoid the fragmentation of previous programmes, this partnership will be set up through one single FPA with several complementary parallel and consecutive Specific Grant Agreements (SGAs) that will carry out the different activities in a common framework. Applications will open on 26th January 2023 and close on 4th April.
The programme will cover the design, development, testing, tape-out of different generations of energy efficient high-end RISC-V processors and/or accelerators, in particular chiplet-based approaches, as well as integration in test-beds and at least one pilot in pre-operational environments in supercomputing centres for user testing and validation.
- Tackling the chiplet clock challenge
- €16m project to secure the chiplet supply chain in Europe
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It also aims to develop the full software stack and the associated software ecosystem for the processors and/or accelerators, addressing the system, middleware and application layers.
It will also explore and exploit existing manufacturing capabilities in Europe, including existing or under development pilot lines, to fabricate the required components, which will be possible with a chiplet approach but will require leading edge processing such as the Intel 4 process in Ireland.
- Intel lights up Irish 4nm EUV scanner
- 1400 RISC-V cores for on-chip machine learning
- Top ten RISC-V articles in 2022
The EPI project has already taped out RISC-V test chips using a 22nm process at GlobalFounrdies in Dresden. This brought together 28 partners from 10 European countries, with a similar goal of making EU achieve independence in HPC chip technologies and HPC infrastructure.
The FPA will also make sure all the IP generated in the initiative stays in the EU and will not be transferred to third countries, dedicating an appropriate effort to IP management, protection and exploitation such as IP licensing and warranties.
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