€8m project for Europe’s first RISC-V supercomputer chip

€8m project for Europe’s first RISC-V supercomputer chip

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By Nick Flaherty

The €8m eProcessor project is using a high-performance Out-of-Order (OoO) processor core based on the RISC-V instruction set architecture as the first high performance computing ecosystem.

The three year project is led by the Barcelona Supercomputing Centre and is supported by Euro HPC funding with a core developed by French designer Cortus and participation from Thales in France and Exapsys in Greece.

eProcessor members Extoll in Germany and Chalmers University in Sweden as well as the Barcelona Centre are also part of another supercomputer chip development using the ARM architecture with RISC-V accelerators for the European Processor Initiative (EPI).

The Cortus RISC-V processor core contributed to the eProcessor project includes full cache coherency to enable large scale systems with a very large numbers of processors for a full scale supercomputer. The design includes adaptive on-chip memory structures and management as well as fault tolerance features and the development spans the full stack from applications to runtimes, tools, OS, and the CPU and accelerators.

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This will use the RISC-V Weak Memory Ordering model in conjunction with fewer memory operations. This allows dynamic execution optimizations which otherwise would not be possible within a Total Store Order approach to improve performance. Optimized implementations of atomic memory operations in conjunction with the cache hierarchy improves the performance of multi-threaded applications such as those which run on a large scale HPC system. 

Unlike the EPI, other optimized versions of the eProcessor are planned for data servers, Artificial Intelligence (AI) for Advanced driver-assistance systems (ADAS) and central automotive CPUs as well as a CPU for mobile phones and embedded applications in the Internet of Things. The higher performance and energy efficiency in supercomputers and the data centre is one reason why Intel is looking at the acquisition of RISC-V pioneer SiFive. 

Other members of the eProcessor project include Idrymas Technologies and Exascale Performance Systems (Exapsys) in Greece and the University of Rome, as well as Christmann and Bielefeld University in Germany.

The eProcessor ecosystem aims to be the first completely open source European full stack ecosystem based on a new RISC-V CPU coupled to a range of accelerators that target traditional HPC applications. The project says it is making use of the full stack (SW and HW) research projects in the  European Processor Initiative, Low-Energy Toolset for Heterogeneous Computing, MareNostrum Experimental Exascale Platform, POP2 CoE, Tulipp, EuroEXA and ExaNeSt.

It will use software simulation, hardware emulation with FPGAs and real ASIC prototypes to demonstrate the full stack feasibility of the hardware and software over the ext foru years 

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