
ECC IP features configurable BCH
Compliant to the ONFI 3.0 electrical interface, the IP is delivered as a GDS II hard macro supporting NV-DDR2 up to 400MT/s. Robust memory subsystem bus design with very high signal integrity and low noise ratio usually requires dedicated and experienced analog circuit designers.
By using its solution, Arasan says SoC designers can now confidently and easily integrate the ONFI 3.0 PHY into their SoC’s with high success rate of first-time working silicon with high ONFI 3.0 data rates.
Arasan’s previously announced ONFI 3.0 NAND Flash Controller IP is designed with Arasan’s patent pending ECC engine with dynamically configurable code-length Bose-Chaudhuri-Hocquenghem (BCH) coders and decoders for high performance and high data rate error corrections.
The patent pending configurable code-length BCH coders and decoders perform the Inversion-less Berlekamp-Massey Algorithm (IBMA) to generate or decode ECC codes on each clock. With Arasan’s code-length configurability, from 1-bit to 32-bits, the BCH coders and decoders can match the target NAND flash error correction requirements; the number of clocks required to generate or decode ECC codes are greatly reduced, thus increasing system performance.
In addition, configurable code-length matching for the target NAND ECC requirement (for example 24-bit ECC) eliminates unnecessary waste of ECC code storage area (i.e. NAND spare area) when compared to using a fixed-code-length ECC engine. With the short code-length in this example, Arasan’s NAND Flash Controller provides the flexibility to use NAND flash with smaller spare area, or to free up the spare area for other purpose.
