EDA design win; Mentor’s emulator used by Barefoot Networks for its 6.5Tbps switch
Barefoot chose the Veloce emulation platform, Mentor says, for its high capacity, virtualization technology, remote access option and track record in networking design verification.
Barefoot Networks is a recent Silicon Valley SDN – software-defined networking – startup that has attracted attention and funding; it describes its proposition as comprising three parts: first, ‘Tofino’, the “world’s fastest switch silicon, that happens also to be programmable”; second, P4, an open source programming language used to write programs for Tofino, and designed clean-sheet for the SDN problem; third, Capilano, the compilers and development tools needed to compile and
debug programs to run on Tofino.
Here’s what Rick Merritt, Silicon Valley Bureau Chief, EE Times, reported on the silicon; Barefoot’s high-end Tofino chip can accommodate flexible configurations of up to 64 100Gbit Ethernet media access controllers or more, slower MACs. It handles all routing functions through Layer 4, assigning one pipeline to every 16 MACs.
In general, SDN processors quickly read packet headers and take actions on them. The chips are “dominated by I/O and memory with a single shared memory buffer and a set of pipelines, so they are very uniform,” said founder and CEO Martin Izzard.
The startup won’t describe just what’s inside the pipelines in terms of look-up tables, packet processors and traffic managers, nor will it give size, power consumption or cost figures for the chip. However it did say it is on par with existing merchant chips. Thus Barefoot’s low-end chip, which handles 32 MACs, should roughly compare to Broadcom’s Tomahawk switch, released in September 2014.
The Tofino chips use both SRAM and TCAM memories. They are made in a 16nm process and can be cooled with standard heat sinks and fans.
“There’s no price premium for our level of programmability, which makes it easy to choose this device,” said Ed Doe, who heads up product marketing for Barefoot.
Barefoot designed two systems to demonstrate the chip—one using the 64-port chip in a 2U top-of rack switch with 65 QSFP ports and a 1U system using the 32-port chip…
…“We thought about building a programmable data forwarding platform that would do for networking what Nvidia did for graphics,” said Izzard. “Switching is a match/action process, and the network workload is very parallel with very little serial dependence, so we set out to build a protocol-independent switch,” he said. (Read full report).
Barefoot Networks benchmarked the different emulators available, and decided the Veloce platform was the only emulator able to handle the large and complex Barefoot Networks design.
“The Veloce emulation platform gave us the capacity we needed to verify our programmable, networking-specific and interconnect-dominated design,” said Dan Lenoski, VP of Engineering, Barefoot Networks. “Beyond the fundamental strengths of the Veloce emulation platform, we were also able to take advantage of their proven hardware+software co-emulation, which is critical for verifying a programmable networking device.”
In the networking space, Ethernet designs are large and particularly intricate, and can tax emulation compile and run times. The Barefoot’s Tofino switch design consists of complex interconnect, which typically creates a challenge for most emulation platforms to route. The Veloce emulation platform uses patented virtual wire technology and the proprietary Crystal2 chip, and had no issue handling the complexity of this interconnect-dominated design.
In addition, the Veloce VirtuaLAB Ethernet used by Barefoot was critical for testing the core functionality of the design. VirtuaLAB includes an Ethernet Packet Generator and Monitor (EPGM) that generates, transmits and monitors Ethernet packets with the Design under Test (DUT); Ethernet testers are modelled in software running under Linux on a workstation connected to the emulator.
Mentor Graphics; www.mentor.com
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