EDA platform tackles nanometer-scale SoC mixed-signal verification

EDA platform tackles nanometer-scale SoC mixed-signal verification

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By eeNews Europe

Offering an intuitive use model and complete reusability of existing verification infrastructure, Symphony delivers up to 5X productivity improvements in mixed-signal verification over traditional flows.

Systems on Chips (SoCs) used in high-performance computing, Internet of Things (IoT) and automotive applications have multiple high-performance, low-noise mixed-signal interfaces. A versatile mixed-signal verification platform is needed to help designers verify connectivity, functionality and performance across mixed-signal circuitry on the chip, which in turn drives a very large number of mixed-signal simulations at the block and top levels. Mixed-signal simulation solutions must be fast, accurate, easy to use and seamlessly integrated into existing analog and digital verification flows to meet time-to-market requirements.

Mentor’s Symphony Platform is built from the ground up to solve these complex mixed-signal verification challenges. Symphony’s modular architecture leverages Mentor’s AFS circuit simulator to provide exceptionally fast mixed-signal simulation performance with nanometer-scale SPICE accuracy and compatibility with all leading digital solvers, including Mentor’s Questa functional verification tool family.

Symphony allows users to remain in their existing use model and maximize reuse of their existing verification infrastructure, including test benches, encrypted IP blocks, and digital/analog netlists. Symphony’s accuracy, performance and intuitive use model, coupled with powerful debugging capabilities and extensive boundary element and configuration support, enable a broad range of verification capabilities including connectivity and functionality checks, as well as mixed-signal IP characterization across A/D subsystems.

Mentor Graphics –

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