EDA tool for automatic generation of IP blocks
The software tool will read process design rules, constraints, and detailed system specifications and automatically generate an IP layout block. The primary goal of the technology is to reduce design time as well as the silicon area of circuits.
“The technology is manufacturing process aware to support older and advanced nanometer processes, making it a flexible tool for IC design firms,” said Danny Rittman, CTO of GBT, in a statement. “An automatic IP layout block generator will offer the capability to create the necessary sub-systems at a very short time, enabling much faster and cheaper IC projects designs.”
No indication was given of how the tool would work or how broadly generic or specialized it would have to be.
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