EDA tool provides integrated memory design and verification
The technology capabilities included with the Cadence Legato Memory Solution improve overall design productivity and comprise:
– Bitcell design and verification environment: engineers can design the bitcell, including variation analysis, without ever having to leave the design environment.
– Memory compiler design and verification environment: users can design and verify full memory arrays within the Legato Memory Solution and access “Super Sweep” technology, that utilizes existing simulation databases for multi-corner and Monte Carlo analysis, to maximize accuracy and simulation throughput for advanced-node designs.
– Memory characterization environment: engineers can create Liberty format models of the memory for system-on-chip (SoC) full-chip analysis. The tight integration between memory characterization and circuit simulation provides additional accuracy and performance improvements that can’t be achieved by point tools.
Cadence; www.cadence.com / www.cadence.com/go/memorysolution
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