EDA tool verifies design rule check decks
DRC deck errors that are found late in the design or after tapeout are very costly, and can cause yield issues, incur additional redesign and mask costs, and ultimately hinder the production schedule.
Using the design rule definition as input, DRVerify generates an exhaustive set of tests that thoroughly checks the correctness and accuracy of the DRC code as it is being developed. When deployed early on, DRVerify accelerates the development of DRC decks and eliminates errors and inaccuracies.
New advanced semiconductor process technologies, at 20nm and lower, come with new design rules that are extremely complex. Implementing DRC checks for such rules is a laborious and error-prone manual programming task, and thus the resulting code can easily have errors and inaccuracies. Yet, it is almost impossible to catch all these errors, since there is no methodical check that verifies that the DRC code exactly reflects its respective design rule description. CAD teams and designers try to create sets of layout test cases exhibiting both "pass" and "fail" conditions and use them to check the DRC deck. Today these tests are usually devised and made manually or assisted by scripts or layout design tools. DRVerify uses the iDRM formal graphical rule definition as its input, and generates test cases based on that input. It systematically searches all boundary conditions of the rule expression and creates every possible variation of the design rule expression that can change the check result. Since it works off the design rule definition source, all its test cases are correct-by-construction. Using a sophisticated layout engine, DRVerify generates thousands of test cases per rule in a matter of minutes.
In addition to verifying DRC decks, DRVerify is also used by design rule manual (DRM) teams to validate DRM design rule specifications.
Visit Sage Design Automation at www.sage-da.com
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
