EDA tools shape custom processor for 3G/LTE Modem
Processor Designer is a tool that allows rapid exploration of processor architectures to optimise for performance, power and area; Fujitsu Laboratories used it for a custom DSP for a multi-mode 3G/LTE modem that delivers higher performance and lower power; a software tool chain automatically generated by Processor Designer enables early software development and debugging.
Traditionally, multi-mode modems have been optimised for power by requiring a hardware block for each mode. By using Processor Designer to develop their own custom-designed DSP, Fujitsu Laboratories was able to develop a processor that handles both 3G and LTE modes.
Processor Designer is an automated, application specific, instruction set processor (ASIP) design and optimisation tool that enables the rapid development of custom processors and programmable accelerators. ASIPs are custom processor cores that deliver the best balance of performance and power for their specific application, while offering flexibility through software programming that is not available in fixed hardware blocks. Fujitsu Laboratories used Processor Designer to achieve a simpler and higher performance design for their 3G/LTE baseband processor, using software running on their custom DSP to handle communications processing instead of implementing unique hardware blocks for each signal processing function.
“Developing a high performance, low power custom DSP for software-defined radio (SDR) demands a solution that provides flexible tools and optimised RTL to achieve increased design productivity and shorter development times,” said Makoto Mouri, research manager of ubiquitous platform laboratories, embedded platform division at Fujitsu Laboratories Ltd.
Processor Designer’s high degree of automation, Synopsys says, enables design teams to focus on architecture exploration and application-specific processor development rather than on creation and consistency checking of the instruction set simulator (ISS), software development tools, and RTL model. The robustness of Processor Designer’s development environment comes from using the Language for Instruction Set Architectures (LISA), a processor description language that incorporates all the necessary processor specific components such as register files, pipelines, pins, memory, caches and instructions. The LISA language enables Processor Designer to use a single processor specification as the source for the automatic generation of the instruction set simulator and supporting software development tools (assembler, linker, and compiler) as well as the synthesisable RTL for implementation. This level of automation enables a top-down design approach for Fujitsu Laboratories, where they can run behavioural DSP functional simulation before generating RTL code.
“Custom processors offer design teams significant advantages over fixed hardware in DSP and embedded vision applications,” said John Koeter, vice president of marketing for IP and systems at Synopsys.
Synopsys; www.synopsys.com/PD
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