EDA tools support TSMC InFO 3D packaging
In particular the system-in-package (SiP) and physical verification system aspects of Allegro have been enabled.
InFO is TSMC’s wafer-level packaging 3D multi-die assembly technology aimed at space constrained mobile and Internet of Things applications. It is a follow-on offering to TSMC’s established CoWoS, a process that has found limited acceptance in the market.
CoWoS – standing for chip-on-wafer-on-substrate – offers high performance but is also high cost. It has been used by Xilinx within its Virtex series FPGAs being used to connect multiple 28nm die via a 65nm interposer. InFO is a similar technology but relaxes the geometry of the interposer to reduce costs and to make assembly easier.
The Allegro SiP design tools and PVS automate the design-rule checking (DRC) flow for InFO design and verification. Cadence tailored the mask-generation technology within Allegro so that it is accurate for InFO design structures in GDSII.
"This integrated tool flow bridges the domains of both IC package design and IC manufacturing, ultimately leading to our overall successful broad deployment of the InFO packaging technology," said Suk Lee, senior director of Design Infrastructure Marketing Division at TSMC, in a statement issued by Cadence.
Related links and articles:
News articles:
CoolCube circuit stacking moves to FinFET process
European 3D TSV Summit to add business focus
Monolithic 3D integration beats next node
Qualcomm to leverage monolithic 3D for smartphones
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
