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Efficiency of half-bridge vs. inverter DC/DC topologies (Part 1 of 2)

Efficiency of half-bridge vs. inverter DC/DC topologies (Part 1 of 2)

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By eeNews Europe



Switching topologies, by their very nature, are more efficient than their linear counterparts. These topologies come in various forms and their components play a significant role in the overall efficiency of the circuit. This article will illustrate the half-bridge and inverter topologies, the end applications, and how their components and component parameters affect overall efficiency.

With the advent of the electronic power switch, in particular power MOSFETs and IGBTs, switching-circuit implementation has been the topology of choice. The main reason for using switching topologies is that when you switch an input voltage with a duty cycle at high frequency, the result is an output whose average value is obtained by filtering.

The filtered switched input voltage results in the desired output voltage of the application; whether it is the output voltage of a point of load converter (POL), the inverter output of a motor drive, or the output of a Class D audio amplifier. Converting the input voltage to an output voltage using switching is significantly more efficient than using a linear amplifier/converter.

Power losses in a switching application are represented as follows (Equation 1):


                                              

which  represents the total losses of a switch (i.e. MOSFET or IGBT), in a switching application.  In a given topology, there are usually one, two, four, or six switches, therefore (Equation 2):

 

where n = number of switches in the topology.

If we compare the losses in a simple linear regulator to a switching point of load (POL) implementation we can see the obvious advantage of the POL .

Linear Regulator

 

Figure 1: Typical linear regulator

Equation 3 shows power loss in a linear regulator, Figure 1.

 

The efficiency of this power supply can be calculated as follows (Equation 4):

where (Equation 4a):

(Note:  This calculation does not include power loss associated with internal bias current in the regulator IC. IC Bias current would result in <1% of additional loss.)

An example of the efficiency of a 12V to 3.3V converter, with 4.2A output current, would yield an efficiency of 27.5%. Obviously, a lot of heat will be generated by this low-efficiency implementation.

Switching Regulator

If we look at a switching regulator in the form of the synchronous buck topology we will see that the efficiency is significantly higher.

 

Figure 2: Typical synchronous buck regulator

Figure 2 shows a typical Synchronous Buck Regulator topology that employs two power MOSFETs (Q1 and Q2) in a half-bridge configuration. The output voltage is (Equation 5):

 

where D = PWM duty cycle.

Switching frequencies for the synchronous buck are in the order of hundreds of kilohertz to a few megahertz. The output filter (L1 & C6) averages the switched input to yield a DC output voltage, Vout. Measurements show the efficiency of this type of regulator to be in the low 90% range.


 

Figure 3: Typical efficiency curve for a synchronous buck regulator

 Figure 3 depicts measured efficiency curves for a regulator similar to the circuit shown in Figure 2 with Vin=12V. Note for the same Vin, Vout and Iout that was used in the linear regulator example, the equivalent efficiency of the switching regulator is 94.5%. This gives a 67% (94.5%-27.5%) improvement over the linear regulator implementation.

There are many ways to estimate efficiency in a switching regulator. One way is to estimate the losses in Equation 1 for each switch, and apply them to Equation 2 and Equation 4.  Both MOSFETs have conduction and switching losses but the switching losses are calculated differently for each switch.

Upper (Control Switch)

 

Figure 4: Loss calculations for the control switch of the sync-buck half bridge

Lower (Sync Switch)

 

Figure 5: Loss calculations for the sync switch of the sync-buck half bridge

Figure 4 and Figure 5 show the equations necessary for calculating the losses in the two FETs. Qg, Qoss, Rds(on), Vf (body diode forward drop) are parameters that are found on MOSFET datasheets. Dead Times (td’s), Vgate, Vin, Vout, f (switching frequency), Iout, D, Igate are parameters that are from the circuit implementation. From these equations conversion efficiency can be calculated.

A second way efficiency can be estimated is through Spice circuit simulation. All that is required are the models for the MOSFETs and the operating condition of the circuit. i.e. Vin, Vout, Iout, fsw, duty cycle, output filter parameters (L, C, Cesr, Lesr) and gate drive voltage and current capability.

Figure 6: Example Spice circuit for efficiency calculation

Figure 6 shows a macro model of a Sync-Buck converter. The feedback and compensation are included to ensure the correct duty and output voltage. The output stage of this model represents a realistic view of the actual application. This includes the MOSFETs and output filter (L1 & C1). R3 represents the load on the converter. There are a number of ways to approach this type of analysis via simulation other than what is shown in the Figure.

For instance, a constant duty cycle could be used to drive the half-bridge that results in the desired output voltage. This would avoid having to include a feedback circuit and would speed up simulation time. 

However trial and error will be necessary in order to find the duty that will ensure the correct output voltage because Equation 5 is only a close approximation of the Vin/Vout relationship. A dead time should always be added to avoid shoot through which will negatively impact the efficiency.

 

Figure 7: Efficiency calculated from Spice macro model

Figure 7 shows the results of simulating a Sync-Buck regulator. The efficiency was derived by averaging the input power and output power over a number of switching cycles during the steady state condition of the output. The plot was generated by performing multiple runs sweeping the output current and calculated the steady state powers and efficiency.

Discrete power loss calculations shown in Figure 4 and Figure 5, as well as simulation, can be used on similar half-bridge topologies. However, switching losses will be calculated differently depending on PWM switching strategy. There are hard switching MOSFET strategies where the power is calculated using the equations in Figure 4. There are soft switching MOSFET strategies, like those found in resonant converters, where the power is calculated using the equations in Figure 5.

(Part 2 will look at inverter designs and power-loss analysis.)

About the author

Dave Divins is a Senior Field Application Engineer at International Rectifier Corp (El Segundo, CA). David graduated from The City University of New York with a BEEE and Binghamton University with a MSEE.  He worked at GE Aerospace as a Systems and Hardware Engineer on Avionic Flight Control and Jet and Turbo Fan Engine Controls. He also worked at Ford Electronic (AKA Visteon) as a Components Engineer and as an Applications Engineer for Synopsis on the Saber Simulator. For the past 11 years he has worked at International Rectifier as a Senior Field Applications Engineer.

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