Efinix uses Cadence to complete Trion FPGA family
The FPGAs have been designed for use in edge computing, AI/ML and vision processing applications and are especially applicable for the mobile, industrial and surveillance markets. The integrated Cadence RTL-to-signoff flow allowed Efinix engineers to achieve first-pass success over a number of nodes down to 10nm. The successful collaboration means that Efinix will continue to use the Cadence flow to grow its Trion product line.
The Efinix Trion product family provides improved power, performance and area (PPA), and the design needed advanced power and area optimization algorithms for a range of nodes. The Cadence digital full flow solution addresses those requirements and provided:
• a unified physical optimization flow from RTL to GDSII with a common UI and database, allowing a seamless transition from physical synthesis to implementation
• a fully integrated place and route, timing signoff and IR drop/power signoff technologies, enabling faster design closure with fewer iterations to speed time to market
“We’re dedicated to continuous innovation, “ said Tony Ngai, founder, CTO and SVP of engineering at Efinix. “Through our collaboration with Cadence and with the strength of their digital full flow solution, we were able to deliver the first wave of Trion family FPGAs in two years, from design start to mass production, successfully optimizing for the smallest silicon geometries to provide the best PPA solution.”
Cadence digital full flow solution includes the Genus Synthesis Solution, Innovus Implementation Solution, Tempus Timing Signoff Solution, Quantus Extraction Solution and Voltus IC Power Integrity Solution.
The Efinix Trion programmable platform delivers PPA advantages over traditional FPGA products. The Trion FPGAs have programmable logic and a routing fabric built on Quantum technology. The fabric has been wrapped with an I/O interface inside a small footprint package. In addition to logic and routing, the fabric features embedded memory blocks and multiplier blocks (or DSP blocks).
The initial phase of the Trion platform has a logic density range from 4K to 200K logic elements (LEs) and standard interfaces such as GPIO, PLLs, oscillators, MIPI, DDR, LVDS, PCI Express, etc
More information
www.cadence.com/go/dffe
Related news
Tensilica Vision DSP doubles vision and AI performance
Cadence releases functional verification IP for USB4
Cadence JasperGold helps Hitachi to comply with IEC 61508 Series SIL 4 requirements
Cadence and Nvidia partner to apply machine learning to EDA
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
