Eight ways to improve RF spurious performance
RF board design is as much about keeping signals out of the places they don’t belong as it is about getting signals to the places they do belong. It requires conscious effort to keep signals isolated to their intended portion of the signal path. Tones, signals, clocks, and all of their harmonic products generated anywhere on the board have a tendency to sneak into output signals as spurs, or worse, into mixers and converters where they get shifted, reflected, and aliased into spurs. Transmit mask requirements mean that even the tiniest spurs can block release of a product.
The importance of spur reduction is compounded by today’s trend towards software-defined radio (SDR) enabled by wideband devices. Because a single platform design can be deployed to address multiple frequency bands, plug-in RF modules are being displaced by larger boards where more signals can interfere with each other. Small plug-in RF modules, including most RF vendor evaluation modules, are completely isolated and exhibit extraordinary spur performance, but use special design techniques. Myriad vias, topside routing, dedicated ground planes, and other layout techniques that work brilliantly for small RF boards often do not scale well.
Low spur RF layout often depends on the intuition of an RF engineer, because layout tools are optimized for large scale layout, not electromagnetic analysis. Usually basic rules are applied during layout and board review, but the real test only comes around once a board has been prototyped and is under evaluation in the lab. After basic board functions, such as power level and linearity, have been checked, evaluation of spurious performance becomes the focus. At this late stage, spurs require the RF engineer, who works the "black magic" to identify a root cause and a fix. Not only is such debug time nearly impossible to predict and schedule, but the fix often involves a board spin, which incurs project delay and expense.
Most of the RF engineer’s intuitive rules are based on simple principles that can be applied during the layout review. Keep these eight rules in mind to get product shipped faster with more predictable schedules.
Rule 1: Place ground vias at ground reference plane switches
Every current that flows along a routed line has an equal return current. While there are many strategies for coupling, the return current generally flows through an adjacent ground plane or in a ground that is routed alongside the signal line. When this reference plane is continuous, all coupling is restricted to the transmission line and everything works great. But when the signal line switches from topside to an inner or bottom layer, the return current must also be given a path.
The situation is illustrated in Figure 1. Current in a signal line on the top layer sees a companion return current immediately below. When it transitions to the bottom layer, the return current goes through a nearby via. However, when there is no nearby via for the return current, it travels to the closest available ground via. The extra distance creates a current loop that acts as an inductor. The interference is made even worse if the undesired current path excursion happens to cross over another line. Another word for a current loop like this: antenna!
Ground reference is the best policy, but, on occasion, a high-speed line may be routed on an internal layer. It is very difficult to place ground reference planes both above and below or pin constraints may force a semiconductor manufacturer to set a supply line next to a high speed line. Any time that a reference current needs to switch between layers or nets that are not DC-coupled, place the decoupling capacitance immediately adjacent to the switch point.
Rule 2: Connect device pads to topside grounds
Many devices include thermal ground pads on the bottom of the device package. On RF devices, these are generally electrical ground and the adjacent pad is dotted with an array of ground vias. Connect the device pad directly to ground pins and to any copper pour through topside ground. When presented with multiple paths, return current splits in proportion to the impedance of the paths. The ground connections through the pad may provide a shorter path or lower impedance than pin grounds.
Good electrical connection between the board and device pad is critical. During assembly, unfilled vias in the array of board vias can also wick solder paste away from the device, leaving voids. Filled vias are one excellent strategy for keeping solder in place. During review, also turn on the solder mask layer to verify that no solder mask is placed on the board ground under the device, because solder mask tends to elevate or float the device.
Rule 3: No reference plane gaps
The immediate vicinity of devices is littered with vias. Power nets break out into local decoupling and then drop to power planes, often with multiple vias to minimize inductance and increase current carrying capacity, while control buses drop to inner layers. All of these breakouts end up thoroughly cramped near the device.
Each of these vias incurs a keepout region, larger than the via diameter itself, on inner ground layers to provide manufacturing clearance. These keepout regions easily create discontinuities on the return current path. Compounding the situation, several vias close together can create a ground plane trench, hidden from view on the top layer CAD view. Figure 2 shows an example of a situation where ground plane clearance from two power plane vias create overlapping keepout regions and create a discontinuity in the return path. Return current is forced to divert around the ground plane keepout regions, creating the now-familiar problem of a radiating inductive path.
Even “friendly” ground vias bring an associated metal pad with minimum dimensions dictated by the board fabrication process. When the via gets too close to the signal line, it can create an encroachment that resembles a mouse bite chomped out of the topside ground clearance. Figure 2 includes an illustration of a mouse bite formation.
Because the keepout regions are created automatically by CAD software and vias are used so frequently on system boards, the initial pass of a layout almost always includes a few return path disruptions. During a layout review, trace every high-speed line, inspecting the associated return current layer for disruptions. A good rule is to move any vias that create a ground layer disruption within any region closer than the top layer ground clearance.
Rule 4: Keep differential lines differential
The return current path is so critical to signal line performance that it should be considered part of the signal path. At the same time, differential pairs are often not tightly coupled, and return currents might flow through an adjacent plane. The two return currents must be routed through electrically equivalent paths.
Even when two lines in a differential pair are not tightly coupled, proximity and shared design constraints keep the return currents on the same plane; really keeping spurs low demands even better matching. Any intentional structures, such as ground plane cutouts underneath a differential component, should be symmetrical. Similarly, length matching may introduce squiggles in the signal line. The return current does not follow the squiggles. Any length matching in a differential line should be reflected in the other differential line.
Rule 5: No clocks or control lines near RF signal lines
Clock and control lines are sometimes treated like benign neighbors, because they operate at slow speed or even near DC. However, their switching characteristic is nearly a square wave, generating distinct tones at odd harmonic frequencies. The radiated energy of a square wave has less to do with its fundamental frequency than the sharpness of its edges. In digital system design, knee frequency estimates the highest frequency harmonic that must be considered, it is calculated through fknee = 0.5 / tr, where tr is rise time. Notice that rise time, not signal frequency, matters. But square waves with sharp corners also have strong high order odd harmonics that might fall at just the wrong frequency and couple onto an RF line, violating an aggressive transmit mask.
Clock and control lines should be separated from RF signal lines with an internal ground layer or topside ground pour. If it is not possible to isolate signals with ground, route lines so that they cross at a right angle. Because magnetic flux lines radiated from the clock or control line form radial cylindrical contours around the flow of current in the aggressor line, they will not induce a current in a receptor line. Slowing a rise time decreases the knee frequency and helps reduce the impact of an aggressor, but a clock or control line can also act as a receptor line. The receptor line can still act as a conduit for routing spurs into a device.
Rule 6: Isolate with ground between high-speed lines
Microstrip and stripline mostly couple to adjacent ground layers. Mostly. Some flux lines still emanate horizontally and terminate in adjacent traces. The tone on one high-speed line or differential pair ends up on the next trace. But a ground pour on the signal layer gives flux lines a lower impedance destination, keeping tones out of neighboring traces.
Clusters of traces carrying identical frequencies, as found routed out of a clock distribution or synthesizer device, may run adjacent, because aggressor tones are already present on the receptor line. But the lines in the grouping eventually spread out. When they do, include a ground pour between the dispersing lines and drop in a via where they begin to spread so that the induced return current can travel back along the nominal return current path. In Figure 3, the via at the end of the ground island allows the induced currents to move onto the reference plane. Space additional vias along the ground pour no more than every tenth of a wavelength so that the ground does not become a resonant structure.
Rule 7: Do not route RF lines over noisy power planes
Once a tone gets onto a power plane, it goes everywhere. Once a stray tone gets onto the supply, buffers, mixers, attenuators, and oscillators modulate on the offending frequency. Similarly, when a supply arrives on a board, it has not yet been cleaned enough to drive RF circuitry. Minimize the exposure of RF lines to the power plane, especially the unfiltered power plane.
Large power planes adjacent to ground create high-quality, embedded capacitance that attenuates spurs and are used in both digital communications systems and some RF systems. Another approach uses minimized power planes, sometimes more resembling a fat trace than a plane, so that RF lines are more easily kept away from the power plane altogether. Both are valid techniques, but never combine the worst features of both, a small power plane with RF lines routed overhead.
Rule 8: Place decoupling close to the device
Decoupling not only helps prevent stray noise from entering a device, it also helps to kill off tones generated inside the device that might otherwise couple onto a power plane. Decoupling capacitance is more effective the closer its placement to the active circuitry. Local decoupling is less hindered by parasitic impedance of board trace and shorter traces create a smaller antenna to radiate the unwanted tones. Place capacitors with the highest self-resonant frequency, generally the smallest value, smallest case size capacitors, closest to the device with progressively larger capacitors moving away from the device. At RF frequencies, capacitors on the backside of the board incur the parasitic inductance of a via in series with the path to ground and lose much of their noise attenuating benefits.
Summary
Board layout review presents an opportunity to identify structures that radiate or receive spurious RF tones. Trace out every single high-speed line and consciously identify its return current path to make certain that it travels alongside the line, checking out transitions particularly thoroughly. Next, isolate potential aggressors from receptor. Follow a few simple, intuitive rules to reduce spurs, speed product release, and keep debug costs low.
References
For more information about designing wireless RF systems and architectures, visit: www.ti.com/bbrfifdr-ca.
About the Author
Peter D. (Duane) Hanish is an applications engineer at Texas Instruments High-Speed Products group where he is responsible for developing wireless communication RF devices and systems. Pete Hanish received a Ph.D. in Electrical Engineering: Systems from the University of Michigan, Ann Arbor. Pete can be reached at ti_petehanish@list.ti.com.
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