Eliyan boosts latest Bunch of Wires chiplet interconnect specification

Technology News | August 16, 2023

By Nick Flaherty

Interconnect & cables

The Open Compute Project (OCP) has launched its latest specification for chiplet interconnect using a ‘bunch of wires’ (BoW).

The BoW2.0 chiplet interconnect specification from OCP is supported by Eliyan in Israel, which has been developing high performance IP. This is an alternative to the PCI Express specification developed by the UCIe consortium.

Eliyan worked with OCP and its Open Domain Specific Architecture (OSDA) to propose the BoW chiplet interconnect approach as a basis for the organization’s multi-die interconnect specification. It recently demonstrated the industry’s first working silicon that is compliant with BoW 2.0 specification (above, back from TSMC). The NuLink BoW PHY, implemented in a 5nm standard foundry process without the need for advanced packaging techniques such as silicon interposers.

The chip operates at 40Gbps/bump delivering over 2.2Tbps/mm of beachfront bandwidth at 130um pitch on standard organic packaging while meeting aggressive power and area targets. The highly area efficient NuLink PHY is bump limited and can deliver up to 3Tbps/mm once implemented on available standard packaging technologies at finer bump pitches by using interference cancellation techniques.

“We support the evolution of BoW in this latest version, which notably doubles the data rate per lane from 16Gbps to 32Gbps, and provides support for configurable directionality, both of which we support in our silicon-proven solution,” said Ramin Fajadrad, founder and CEO of Eliyan.

“As a foundational contributor to this effort, and the first company to demonstrate compliance with the latest specification in a working chip, we are excited about the potential for the BoW die-to-die interconnect method to advance the capabilities of high-performance computing and memory efficiency in key applications such as Generative AI,”

Farjadrad is an inventor of the original interconnect technology behind BoW, which he proposed to OCP in 2018 and it was used as the basis for the development of the initial specification of the standard.

Eliyan specifically developed the BoW on standard packaging to address the need for highly efficient die-to-die PHYs to connect large number of chiplets with different functions in one package, which is critical for realizing the scale of performance and integration required by compute-intensive applications in data centres, cloud computing, and, most importantly, artificial intelligence. Farjadrad’s experience also includes pioneering work in creating connectivity technologies such as PAM4 SerDes, Multi-Gbps Enterprise Ethernet, and Multi-Gbps automotive Ethernet that were eventually adopted as IEEE standards.

“Eliyan has demonstrated a commitment to addressing the critical challenges the high-performance computing industry faces as it applies next generation architectures and to the evolving needs of OCP members in cloud computing, data centers, edge computing and AI processing. We welcome their development efforts to demonstrate 5nm silicon proof of a PHY compliant with the BoW 2.0 specification for chiplet connectivity and look forward to their continued contributions to the Open Chiplet Economy,” said Bapi Vinnakota, OSDA Lead at OCP.

The UCIe consortium recently released its 1.1 specification, based around the PCI Express and CXL interconnect standards and supported by Intel, Advanced Semiconductor Engineering, AMD, ARM, Qualcomm, Samsung and TSMC as well as Verisilicon and Avery. The specification provides a complete standardized die-to-die interconnect with physical layer, protocol stack, software model, and compliance testing to enable end users to easily mix and match components to boost that chiplet economy.

www.eliyan.com