Eliyan ports chiplet interconnect to Samsung 4nm process
Eliyan has taped out of its NuLink chiplet on Samsung Foundry’s SF4X 4nm following a test chip on TSMC’s 3nm process.
The Nulink PHY in a x64 UCIe Advanced Package Module will see initial silicon for characterization in Q1 2025.
The high-performance chiplet interconnect supports up to 40Gbit/s bandwidth using advanced packaging micro bumps at 45-micron pitch and offers the industry’s lowest power density. The Bunch of Wires (BoW) implementation is fully compatible with the UCIe standard for die-to-die and die-to-memory chiplet connectivity performance on standard as well as advanced packaging.
Eliyan will use the technology for building custom High Bandwidth Memory (HBM) base dies and offer it as IP to enable ASIC disaggregation approaches using chiplets. The performance and power of the solution allows it to support multi-die designs that address the memory and IO walls common in GenAI subsystem-level designs.
“Samsung Electronics is a recognized leader in advanced foundry logic process for GenAI and HBM chips used in tomorrow’s data centers,” said Paul Cho, Corporate EVP of Products and Solutions Planning at Samsung Electronics. “Eliyan’s technology enables Samsung’s customers to fully leverage its process technologies and memory products to their fullest potential.”
“We see custom HBM4 base die as a critical piece of all future AI systems for both training and inference of GenAI/LLMs. Our NuLink PHY technology meets the stringent power and thermal density requirements to enable the highest performance connectivity between XPUs and HBMs and provide the needed reliability and scalability,” said Eliyan’s co-founder Patrick Soheili
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