Eliyan raises $40m to shake up chiplet interconnect
US startup Eliyan has raised $40m to commercialise a chiplet interconnect technology that has the potential to dramatically reduce the cost of high performance, high density chip designs.
The company has already taped out its technology on TSMC’s standard 5nm process and is developing a design for 3nm.
The NuLink technology is a bidirectional low latency SERDES serial/deserialiser block that allows high speed interconnect on organic substrates. This avoids the needs for silicon interposers and allows more chiplets to be placed on larger substrates more cost effectively.
The company’s founding CEO Ramin Farjadrad is the inventor of the innovative and proven Bunch of Wires (BoW) scheme, which has been adopted by the Open Compute Project (OCP). NuLink technology is backward compatible with Universal Chiplet Interconnect Express (UCIe), a standard developed by Intel and donated to the UCIe Consortium as the mainstream chiplet interconnect.
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The 32Gbit/s technology can be integrated into ASICs, and is designed to fit under a solder bump so that it does not take up usable silicon real estate.
“If we sit on both sides of the link we don’t need a silicon interposer,” Farjadrad told eeNews Europe. “Every wire can carry signal in both directions with signal cancellation, so you can stay with NRZ [modulation] rather than going to PAM4 with equalisation and forward error correction (FEC),” he said. “This enables us to double the bandwidth and stay at low power. The power is similar to advanced packaging with 30% of the power and 2 to 4x higher bandwidth. It is easy to port because the design is done in such a way as to have minimal analog blocks, just one, and everything else is digital.”
Farjadrad is also planning to develop small converter chips that can be added alongside chips to provide the chiplet interconnect. These NuGear chips are intended to be added alongside HMB high speed memory chips to allow more devices on a substrate and improve the reliability by reducing the thermal effects.
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“We have plans for three of four of our own chiplets these could be from 3 up to 16nm depending on the end application and that’s why the porting needs to be simple,” he said.
“This would be 2mm x 8mm chiplet that acts like a gearbox to provide the bandwidth over the Nulink,” he said. This would allow more HBM memories around the ASIC, staggering the memory on the substrate to give four times the capacity and four times bandwidth.
The NuGear chiplet also increases the separation of the chips from 0.1mm to 2mm, significantly reducing the thermal issues. This can also be used with photonic chips, he says.
Eliyan’s Series A round was led by Tracker Capital Management, which was founded by Stephen Feinberg, Co-Founder and Co-Chief Executive Officer of Cerberus Capital Management. Celesta Capital and other strategic investors including Intel Capital and Micron also participated. As part of the investment, Dr. Shaygan Kheradpir of Cerberus, former Group CIO and a founding member of the Executive Leadership Committee at Verizon, will join the Board of Directors of Eliyan.
The company’s first silicon is expected in the first quarter of 2023. An earlier version of the NuLink technology has been mass produced on a 14nm process, validating its commercial viability and performance.
Dr. Shaygan Kheradpir of Cerberus commented: “Traditional methods of integrating multi-chip architectures impose challenges that result in high costs, low yield, manufacturing complexity, and size limitations. Eliyan has drawn upon its years of experience to develop a practical scheme that is also backward compatible with existing standards to chiplet interconnect and is optimized for delivering the necessary high bandwidth, low latency, and low power capabilities. We are confident its NuLink technology holds the key to a broader proliferation of chiplets in key market sectors such as hyperscalers, AI processor development, high-performance memory, and advanced graphics chips.”
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