Embedded instrumentation for high-speed RAM access test
Users can use this new method to close significant holes in fault coverage affecting the test of modern electronics. Thanks to a complete system integration of ChipVORX IP, the recognition of structural connections between the RAM targets and the FPGA as well as the test program generation (ATPG) and − in the case of detected defects − the pin-level diagnostics are fully automated. The test itself is based on access through a standard IEEE 1149.1 TAP (Test Access Port) and can be executed on any System Cascon run-time station without additional options, with full support of Gang applications. Since ChipVORX IP is target independent; the types of supported RAM devices are not limited.
In addition to any kind of static RAM, modern DDR-SDRAM devices are supported. Since the same system libraries are utilised as with normal Boundary Scan based memory access tests, users can create new RAM models at any time, too. Currently, ChipVORX models for RAM Access Test are available for all Altera and Xilinx FPGA families, with others in development. The use of ChipVORX IP does not require any background knowledge nor any special FPGA tools or recurring IP modifications.
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