Embedded tool automates clock signal testing
ESA technologies – this term encompasses Boundary Scan, Processor Emulation Test, In-System Programming, Core Assisted Programming and Chip Embedded Instruments. The latter ones represent the counterpart to conventional test and measurement instruments. In contrast, it enables on-chip testing without invasive methods such as test leads or contacts. Goepel electronic is driving this technology through its offering of frequency-measaurement FPGA soft macros. The company’s ChipVORX modular IP controls Chip Embedded Instruments. Goepel’s portfolio enhancements enable FPGA-assisted tests of differential clock signals and measuring frequencies within the application. Thus, users can verify signal dynamics and improve test coverage in a software-controlled workflow. Since the process does not require FPGA design synthesis, it is possible to adapt the test process dynamically to changing requirements, such as operative hardware debugging of diverse signal pins. This particularly relevant for sophisticated FPGA designs with Gigabit interfaces involved.
The ChipVORX IP for universal frequency measurement configures an appropriate instrument inside the FPGA, which is controllable by the user via the standard IEEE 1149.1 TAP. In addition to frequency measurement, a counter function is also available. These features allow verification of clock signals as well as detection of pulses, non-deterministic signal changes or stuck-at-0/1 errors. Whereas the control for automated production test is realised in the context of the test program, the interactive debugging can access graphic panels. Running the program is possible on any run time station without further options. Gang Applications are supported as well. Test procedures can be generated automatically by means of an integrated Automatic Application Program Generator (AAPG).
For more information visit www.goepel.com
Read also
Multi-function boundary-scan testers cover all bases
Single chip integrates JTAG standards and mixed-signal test instruments
Revised IEEE 1149.1 ‘JTAG’ standard should reduce IC design costs through test re-use
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
