EMC – Synonym for Exasperating, Magic, Confusing? – Part 2
Equivalent circuit model of the capacitor
In the capacitor’s equivalent circuit model, the simplest model comprises just a serial connection of the nominal capacitor, an equivalent series resistance and a parasitic series inductance. The ESR determines the lowest impedance reached at the capacitor’s series resonance. Above this series resonance the capacitor’s impedance will increase with frequency, thus behaving like an inductor. A more sophisticated model would also include the components Cp and Rp, connected in gray in figure 1. Modified equivalent circuits are also found in literature which show Cp and Rp in parallel to the whole serial connection of (desired) capacitor, ESR and parasitic inductance; it is merely a question of transforming the values of the respective inherent components. The parasitic inductance together with Cp leads to a parallel resonance that is frequently neglected, because such parallel resonance of typical SMD ceramic capacitors will only appear at several GHz.
Figure 1. Equivalent Circuit of a Capacitor
Figure 2. Equivalent Circuit of a Resistor
The series resonance of the capacitor is determined by its type (electrolytic, foil, ceramic), mechanical dimensions (axial, radial, SMD, size) and of course its value. The higher the capacitance of a certain capacitor type, the lower the series resonance frequency. Therefore it is advisable not just to place a single capacitor for decoupling purpose, but combine two or several caps to achieve broadband decoupling. For example, it is often recommended to pair a 10nF capacitor for lower frequencies with a 100pF cap for higher frequencies. The following will explore whether this is advisable. A very basic linear RF simulation tool is sufficient for demonstrating this; there are even freeware tools available for this purpose. Many manufacturers of ceramic capacitors supply S-Parameter files for their products and it is advisable to use them. Figure 3 shows the attenuation of the above two capacitors when placed in parallel from a 50Ω track to GND.
Figure 3. Attenuation of 2 Ceramic Capacitors of 10nF and 100pF in Parallel in a 50Ω System
This looks quite acceptable. Attenuation of at least 30dB was achieved for frequencies between 20MHz and well above 1GHz. If a higher reference impedance than 50W had been used, it would look even better. In a rather ideal world, it would be possible to stop here. But has something been overlooked? In reality, it is not possible to connect the capacitors perfectly to GND or to the track or pad which needs to be decoupled. Every track on the PCB above behaves like a transmission line and its impedance is determined primarily by track width, the thickness of the PCB or, in case that a multilayer PCB is used, the distance between signal and GND layer, the distance to adjacent GND areas and the dielectric constant er of the PCB material. Again, there are special books and free calculation tools available for guidance on this issue. With track widths of 0.2mm, GND area >0.5mm away from the track and er = 4.7, impedance of well above 100Ω for 2-layer boards (1.6mm standard thickness) will result and close to 50Ω will result for a multilayer board with 150µm distance between signal layer and GND plane.
When considering the red curve in figure 4, it is obvious it looks quite different from the previous graph. Figure 4 shows how decoupling performance changes if the board layout is not done with care. The assumptions for the red curve were as follows: standard 2-layer PCB, distance between caps and to their GND vias: 10mm with just one GND via per cap. Now, quite unexpectedly, there is a highly undesirable resonance around 130MHz with attenuation of only 6dB. The green graph in figure 4 shows the performance for an improved board layout: Now a multilayer board is used, the two caps are closer to each other and each one has two GND vias only 1mm away from the respective cap. The resulting decoupling performance is significantly improved, but there still seems to be room for improvement.
The lesson learned from this example is, first, the decoupling caps need to be as close as possible to each other and to the component which needs to be decoupled. Secondly, using a multilayer PCB with a GND plane just below the signal layer is beneficial too. And, finally, it appears to be a good idea to do some simulation with “real” capacitors rather than just selecting them based on instinct. Innovative layout designs even place only a single centralized group of capacitors to decouple a larger area – but that is something which should not be attempted without careful simulation.
Figure 4. Attenuation of 2 Ceramic Capacitors of 10nF and 100pF in Parallel in a 50Ω System with Realistic Parasitic Components in Connecting Tracks
Red: Distance between caps and to their GND vias: 10mm, one GND via per cap, track width: 0.2mm, board thickness top to GND: 1.6mm.
Green: Optimized, distance between caps: 5mm, between caps and their GND vias: 1mm, two GND vias per cap, track width: 0.2mm, board thickness top to inner GND plane: 0.15mm
As mentioned previously in this article, car manufacturers are aware that EMC issues generally become costlier the later they are discovered. Engineers may benefit from this insight within their own development work. Giving some thought to EMC behavior already when designing a circuit definitely helps avoid unpleasant surprises during EMC approval testing. Having said that much – what needs to be done if a design fails EMC testing despite the care exercised prior to testing? Or, just in case it was not possible to include sufficient time, budget or experience appropriate for EMC assessment in a project, what can be done to improve matters?
The truth is that no standard procedure exists. If emission is the problem, a probe across the circuit can be attempted with a field probe to detect any potential “hot spots.” Or, if fast enough, it is possible to re-perform the particular failed emission measurement while connecting a short isolated wire to some “suspicious” spots on the PCB. If a critical one shows up, the number of spurs will increase; this becomes immediately noticeable on the connected receiving instrument. If the design performs weakly in terms of susceptibility, consideration must be given to what parts of the circuit are affected (this can often be deduced from the malfunction occurring during the immunity measurement), and the coupling path must be located. Once the critical parts of the circuit have been pinpointed, the techniques described above can be used to improve EMC performance. A key consideration in this regard is that effective decoupling requires a solid GND area. If this is lacking, it may be easier to redesign the board first; alternatively some copper foil could be added to facilitate further optimization measures in the lab.
Hopefully it has become apparent that there is nothing magical at all about EMC and that it is simply applied physics. Naturally, our knowledge about coupling mechanisms and particularly their parameters tends to be inaccurate and sometimes incomplete, even if highly sophisticated electromagnetic simulation tools are used. So there is a trace of magic (or uncertainty) left in the process after all. But these imponderables are also what challenge us daily in this specialized discipline.
Juergen Strohal is Senior Applications Manager at semiconductor manufacturer Atmel. He is responsible for hardware applications at Atmel Automotive in Heilbronn, Germany. Besides managing the hardware applications team he is in charge of customer support as regards electromagnetic compatibility of Atmel’s automotive ASSPs.
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