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Energy efficiency through adaptive voltage scaling

Energy efficiency through adaptive voltage scaling

Technology News |
By eeNews Europe



System energy efficiency is heavily dependent on microprocessor power consumption. Moore’s Law and ever-increasing computing capacity is driving chip power consumption increasingly higher, despite smaller silicon geometries and lower supply voltages, so it is crucial to minimize the power consumption of every chip on every board in every instance to facilitate low energy consumption at the system level. Besides the important environmental impact of energy consumption, it is a practical necessity in extremely high-power-density data centers where the cooling of silicon is becoming increasingly difficult.

A common way of minimizing silicon chip power consumption is to change frequency and supply voltage based on the need for computing power over time. A lower supply voltage is highly effective in reducing power and energy consumption as power dissipation is proportional to the square of the supply voltage. If the demand for computing power is low, the clock frequency of the microprocessor can be decreased; and when the clock frequency is lower, the supply voltage can also be lower. This technique is called dynamic voltage scaling (DVS) and is commonly implemented by an open-loop approach where pre-determined combinations of frequency and supply voltage are stored in a look-up table.

DVS offers much better efficiency compared to fixed voltage supply and facilitates a great deal of energy saving, but does not fully utilize the potential of voltage scaling. Shortcomings of DVS include the necessary voltage margins to guarantee safe operation taking into account the static and dynamic regulation window of the power supply, and also the silicon process variations and operation within different environmental conditions.
 
Adaptive Voltage Scaling

Adaptive voltage scaling (AVS) deals with the shortcomings of DVS via a closed-loop real-time approach that adapts the supply voltage exactly to the minimum required voltage for the actual clock frequency and workload demand of the individual processor chip. It also automatically adjusts to compensate for process and temperature variations in the processor.
 
Modern high-performance microprocessors change workload and operating conditions within nanoseconds –therefore real-time regulation of the microprocessor supply voltage puts a high demand on control-loop bandwidth and requires close monitoring of computing hardware performance in the feedback loop. This is now possible with the recent release of AVS controllers that include dedicated IP and hardware.


 
Typical differences in energy consumption between fixed supply voltage, DVS and AVS are shown in Figure 1. Note that lowering the frequency alone does not affect the energy consumption. The average power will decrease but lower clock frequency means that a specific computing task takes longer time, e.g. if the frequency is lowered to f/2 the computing time will be twice as long. The supply voltage must be decreased to realize energy savings.

 

Figure 1. Comparison of energy savings in a microprocessor with fixed supply voltage, DVS and AVS
 
The feedback loop includes the board mounted power supply (BMPS) and is based on monitoring the computing performance of the processor chip, effectively eliminating any excess voltage margin associated with DVS. Because it actually senses the voltage directly on the chip, the loop also provides the ultimate remote sense connection for the voltage regulator feedback. This also has the effect of eliminating any voltage error due to voltage differences in the ground plane between the BMPS and the microprocessor.
 
The supply voltage is also further reduced because the BMPS static and dynamic output inaccuracy is automatically accounted for in the feedback loop. All together these reductions minimize the chip supply voltage, resulting in dramatic energy savings in the processor because the power and energy consumption is proportional to the supply voltage squared. An interesting and very important feature of AVS, besides optimizing energy management, is that the silicon junction temperature is minimized while also maximizing available computing power.


Implementation of AVS

AVS is implemented at the board system level and includes components in the microprocessor and the BMPS. To facilitate AVS, both the microprocessor and the BMPS must be designed to support it, including the necessary functional blocks or interfaces. The feedback loop is controlled by a microcontroller on the processor chip that communicates with the BMPS control circuitry via a command protocol. In conjunction with BMPS, the microcontroller contains the necessary IP and hardware to automatically handle the procedures for scaling the supply voltage to the required clock frequency and demand for processing capability, which normally should make system integration quite simple.
 
An example of the AVS control loop and the different functional blocks in the system are shown in figure 2. The advanced power controller (APC), licensed by National Semiconductor, integrates a hardware performance monitor (HPM), which provides the AVS loop control and the voltage scaling commands to the slave power controller (SPC) in the energy management unit (EMU), i.e. the BMPS that provides the regulation of the supply voltage. The PowerWise interface (PWI) is an open-standard two-wire serial interface and provides the necessary command protocols for AVS. The APC handles all aspects of voltage control, and has the ability to actively scale the supply voltage to minimize the power and energy consumption of the microprocessor.
   

 
Figure 2. The AVS and its functional blocks
 
Modern state-of-the-art microprocessors are based on advanced silicon chip and SoC (system-on-chip) technologies with several cores, accelerators and interfaces that require different supply voltages. Multiple AVS feedback loops are then used for energy management to minimize the energy consumption of each element.


 
AVS and Digital Power
 
Digital power devices, e.g. BMPS with digital control and digital interfaces are very suitable for use with AVS techniques. Digital power devices already include digital interfaces that can be used for AVS and also facilitate the regulation bandwidth required to fully benefit from AVS. This is further emphasized with the recent introduction of PMBus Power System Management Protocol Specification V1.3, which provides a standardized method of communication to power conversion and power management devices and also includes a dedicated bus to statically and dynamically control processor voltages facilitating AVS. PMBus V1.3 also includes higher speed communication to minimize latencies in the AVS control loop.
   

Figure 3. PMBus V1.3 with a dedicated AVS bus
 
PMBus is the standard digital protocol for communication with power devices like BMPS and PMBus V1.3 is projected to be an important bus standard for manufacturers of FPGAs, ASICs and microprocessors for computing and networking applications, and many other types of multi-core-based processors that will benefit from AVS. A good example of state-of-the-art digital BMPS is Ericsson Power Modules’ BMR464, which features digital PWM control and non-linear transient response and is fully PMBus read and write compliant, offering an excellent choice for integrating AVS at the board system level.
 

Figure 4. Ericsson Power Modules’ BMR464 digital BMPS
 
Adaptive voltage scaling is a powerful technique that optimizes supply voltages and minimizes energy consumption by modern high-performance microprocessors. It will minimize power dissipation and silicon junction temperature at all times, thereby reducing system energy consumption and increasing system reliability. All together it makes AVS a highly valuable technique for system integrators in their ongoing pursuit to reduce end-users’ total cost of ownership (TCO).

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