Energy-efficient FPGA acceleration takes only 2.15×2.55mm

Energy-efficient FPGA acceleration takes only 2.15×2.55mm

New Products |
By Julien Happich

The new chip delivers eight times more memory (1.1 Mbit RAM), twice the digital signal processors (8x DSPs), and improved I/Os over previous generations. Well suited to support voice recognition, gesture recognition, image recognition, haptics, graphics acceleration, signal aggregation, or I3C bridging, the iCE40 UltraPlus brings added intelligence to smartphones and IoT edge products, such as wearables and home audio assisted devices, in a package as small as 2.15×2.55mm.

The MHC paradigm is concentrated around a highly energy-efficient method for computing algorithms quickly and locally using dissimilar processors to offload power hungry application processors (APs) in battery-powered devices. More DSPs offer the ability to compute higher-quality algorithms, while increased memory allows data to be buffered for longer low-power states. The flexible I/Os enable a more distributed heterogeneous processing architecture. This combination provides flexibility to enable OEMs and the Maker market to quickly deliver key innovations, such as always on sensor buffers and acoustic beam forming. The device draws less than 100 micro watt in standby.

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