Energy-harvesting memory IC pioneer preps TSMC test chip
Metis Microsystems Inc. (New York) is preparing to demonstrate functional circuits that harvest energy from transient data, by way of a TSMC multiproject wafer.
Metis develops novel memory and logic circuit architectures that harvest charge from transient on-chip data and claims these could provide order-of-magnitude improvements in the energy-delay product at the component level of CMOS memories. Also claimed are improvements in the reliability of bit-cell transistors and in their read and write noise margins. Proposed self-limiting, self-disabling and self-regulating harvest circuits also enable CMOS memories to eliminate much of the energy and performance inefficiencies from bit-cell transistor variability creating opportunities for AI and networking hardware to deliver higher compute performance with limited energy or heat removal resources.
The CEO of Metis is Azeez Bhavnagarwala, previously a research engineer with Arm, AMD and IBM who has been working on the technology since founding Metis in 2017 (see Metis emerges with ‘data-is-energy’ IP). Bhavnagarwala is also a lecturer in chip design and computing systems architecture at New York University.
Bhavnagarwala told eeNews Europe that the production of a 16nm FinFET silicon demonstrator by TSMC will be a major milestone for Metis – as will the completion of a full suite of US and international patents. He added that Metis is seed-funded by family and friends for now, but the company has been speaking to potential IP licensors and pursuing grants from US government agencies.
Don’t dump the charge
Bhavnagarwala said that parts of the traditional memory circuit design are based on legacy ideas that have declined in relevance as voltages have declined, as noise and variability has increased and power consumption become more critical.
Rather than simply dumping bit-transition current to ground, as is the case in conventional CMOS circuits, Bhavnagarwala has proposed the use of dynamic circuits with a charge harvest node. The ability to retain charge provides multiple performance and energy efficiency benefits, he said. He has proposed circuits for Register File (RF), 6T SRAM, ternary content addressable memories (TCAM), compute-in-memory arrays and non-volatile memories such as MRAM
Based on a 16nm FinFET manufacturing process, simulations show these circuits can lower active energy along local and global bit paths by 5X while also more than doubling their circuit speed, he claims.
SRAMs and register files
The types of circuits that will be on the test chip are arrays of six-transistor SRAMs as they are typically used in L2 and L3 cache memories and register files, Bhavnagarwala said.
Bhavnagarwala emphasized that with the ability to harvest charge from bit transitions designers will be able to get the double win of improved performance and lower power consumption at the same time. “The implementation of proposed circuits avoids complexities that are associated with overheads in performance, energy consumption and silicon area. For example, use of available metal tracks to hold harvested charge makes it readily available to drive concurrent 0 to 1 bit transitions,” he said.
Comparison of register file arrays with identical architecture, bitcell, 16FF parameter decks but different peripheral circuits – proposed versus industry-typical. Source: Metis Microsystems Inc.
Bhavnagarwala said Metis is working with Muse Semiconductor LLC (Aurora, Colorado), a specialist in managing multiproject wafer runs for TSMC. “We hope to get the tape out done in time for a shuttle in 4Q23, if not it will be 1Q24,” he said. Participants usually get their test chips back within about three months from such MPW runs.
Bhavnagarwala said that Metis is working on what is primarily a digital offering that is well suited to in-memory computing either using SRAM or potentially non-volatile memory. The tremendous interest in the computational demand of generative AI together with concern over power consumption could provide a key opportunity for Metis, he said. No changes are required within the bit cell, to the CMOS process, or to operating voltages, Bhavnagarwala said.
“We have one commercial company that is helping us apply for grants that has said that if the test circuits perform as we expect they will license the technology,” Bhavnagarwala said, but he declined to name the company at this time.
Related links and articles:
News articles:
Metis emerges with ‘data-is-energy’ IP
ReRAM could perform as battery, says Leti
SureCore to help UK ReRAM startup come to market
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
