Espressif moves exclusively to RISC-V

Technology News |
By Nick Flaherty

Low cost microcontroller system-on-chip Espressif Systems is moving exclusively to the RISC-V open source instruction set architecture. The company has previously used the Tensilica Xtensa configurable core from Cadence Design Systems.

The move was confirmed by Teo Swee Ann, CEO and president of Espressif Systems, based in Shanghai, China.  

The company has just launched an RISC-V SoC with stacked flash memory for the Matter home automation protocol.

The ESP32-C2 (above) is a combo WiFi-BLE chip that stacks the flash memory to reduce the size of the package. “It was conceived middle of last year, at the start of the Great Semiconductor Supply Shortage, which to a certain extent, persists till today,” said Ann “Hence, one of the most important goals of the chip is to reduce its silicon area and the flash size requirement [for] simple high volume, low data rate IoT applications such as smart plugs and light bulbs.”

All the C and H chips will be based on RISC-V.

The C2 chip is in a 4mm x 4mm package, supporting WiFi 4 + BLE 5.0 with 272 kB of memory and runs ESP-IDF and frameworks such as ESP-Jumpstart and ESP-RainMaker. The ROM code is optimized to reduce the need for flash. ESP-IDF is Espressif’s open-source real-time operating system for embedded IOT devices and is supported by Espressif and the community for all ESP32 chips.

The smaller package and die enhance the RF performance due to reduced stray parasitics. The ESP32-C2 can transmit 802.11N MC7 packets (72.2 Mbps) with 18 dBm output power. It transmits at the full 20 dBm FCC limit for the lower data rates. The typical receiver sensitivity is between -97 to -100 dBm for 1 Mbps 802.11B packets and the receive current is 58 mA.

Related articles

Other articles on eeNews Europe



Linked Articles
eeNews Europe