Ethernet and UALink IP connects massive AI accelerator clusters
Synopsys has announced the industry’s first Ultra Ethernet and UALink IP, including controllers, PHYs, and verification IP, to meet the demand for standards-based, high-bandwidth, and low-latency HPC and AI accelerator interconnects.
As hyperscale data center infrastructures evolve to support the processing of trillions of parameters in large language models, they must scale to hundreds of thousands of accelerators with highly efficient and fast connections. Synopsys Ultra Ethernet and UALink IP will provide a holistic, low-risk option for high-speed and low-latency communication to scale-up and scale-out AI architectures.
“For more than 25 years, Synopsys has been at the forefront of providing best-in-class IP that enables designers to accelerate the integration of standards-based functionality,” said Neeraj Paliwal, senior vice president of IP product management at Synopsys. “With the industry’s first Ultra Ethernet and UALink IP, companies can get a head start on developing a new generation of high-performance chips and systems with broad interoperability to scale future AI and HPC infrastructure.”
Advanced capabilities of the new Synopsys Ultra Ethernet IP include:
- IP to scale out backend networks: Consisting of PHY, MAC and PCS controller, and verification IP, the Synopsys Ultra Ethernet IP solution offers a low-risk path for designers developing systems that can support up to one million endpoints in a single network.
- Best-in-class 224G Ethernet PHY IP: The silicon-proven Synopsys 224G Ethernet PHY IP, which supports the Ultra Ethernet protocol, has demonstrated broad interoperability as shown at multiple tradeshows including ECOC, OFC, and DesignCon.
- Patented error correction implementation: The Synopsys Ultra Ethernet MAC and PCS controller IP provides up to 1.6 Tbps of bandwidth with ultra-low latency, enabling the real-time processing needed for AI workloads.
- Seamless integration: The MAC and PCS IP support an interface to the higher layers of the Ultra Ethernet stack providing a full silicon implementation for switches, AI accelerators and smart NICs.
- Accelerated verification and validation: The Synopsys Ultra Ethernet verification IP helps ensure protocol adherence to rapidly evolving standards, enabling faster and more efficient validation of AI and HPC systems.
“Juniper has already introduced the industry’s first 800GbE capability with its PTX10002-36QDD Packet Transport Router, which utilizes our proprietary Express 5 ASIC with Synopsys Ethernet IP,” said Debashis Basu, senior vice president of Juniper Engineering. “We will continue to partner with Synopsys and leverage the latest technologies from the Ultra Ethernet Consortium (UEC) to transition into the 1.6TbE era. This indicates our ongoing innovation in high-speed networking to achieve our goal to significantly improve scale, reliability, and performance in data center networks. This is particularly important as AI workloads continue to grow exponentially, making such networks much more efficient and cost-effective.”
Advanced capabilities of the new Synopsys UALink IP include:
- IP to scale up computing fabrics: Consisting of PHY, controller, and verification IP, the Synopsys UALink IP solution speeds time-to-market for designers developing systems that can support up to 1,024 AI accelerators.
Efficient, high-speed data transfers: Engineered for data-intensive AI workloads, the low-power and high-bandwidth Synopsys UALink PHY IP provides 200 Gbps per lane. - Latency-optimized with memory sharing capabilities: Synopsys UALink Controller IP helps
mitigate critical bottlenecks of AI hardware infrastructure via shared memory access from accelerator to accelerator. - Built-in protocol checks: The Synopsys UALink Verification IP, combined with Synopsys hardware-assisted verification solutions, provides quick and reliable verification for AI hardware.
“Synopsys has decades of expertise in contributing to the industry’s essential interconnect standards and in delivering widely adopted high-speed interface IP,” said Kurtis Bowman, chairperson of the board at UALink Consortium. “We appreciate Synopsys’ commitment to enabling UALink IP to create a scalable, high-performance data center ecosystem for designers to meet the growing demands of AI models.”
The Synopsys Ultra Ethernet IP, including MAC and PCS, PHY, and verification IP, is scheduled to be available in the first half of 2025. The Synopsys UALink IP, including controller, PHY, and verification IP, is scheduled to be available in the second half of 2025.
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